Latest threads in Field-Programmable Gate Arraysshow only best voted threads
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ps2 mouse protocol
Hi, I'm trying to communicate with the ps2 mouse. So I first force the ps2c line to '0' for 100us. Then I force the ps2d line to '0' and ps2c to high impedance. Now the mouse should take over the ps2c...
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15 years ago
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Does anyone have sdio protocol experience?
I am trying to write an sdio host controller. sdio is an extension to the sd/mmc protocol used on memory cards. It is used for pda peripheral devices, for example. Note that this question is about the...
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15 years ago
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DSP48 Inference Template for XST
I'd like to infer a DSP48 in XST and can't find a template that will infer all of these opmodes: P=M P=M+C P=P+M P=P-M (where M=A*B) I can get XST to do any of these, one or two at a time, but when I...
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15 years ago
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NGC / EDIF Viewer
Suggestion: if you are using XST (or any other synthesis tool) and have Xilinx's PlanAhead, you can bring in an NGC/EDIF and view the schematic with PlanAhead's viewer. I just started using it and...
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15 years ago
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FPGA dev kit with 4-8 Cyclones or Spartans
Hello. We need a boards with 4 or 6 or even 8 identical FPGA chips installed, each one should be mid-range Altera Cyclone II or III, let say, each chip should contain between 30.000 LEs and 60.000...
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15 years ago
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Call VHDL module from Verilog
Hi, I have a basic question. Is is possible in the xilinx ISE enviroment to make a verilog wrapper of some VHDL code. I don't want to recode it in verilog. Thanks Rob
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15 years ago
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Getting started with VHDL and Verilog
Hi all, My background is in Software Engineering C,C++,Java and Unix. I am getting started with VHDL and Verilog. What is the good way/books/ websites/training to get started? I have B.S. and M.S. in...
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15 years ago
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warning from ISE 9.2
Hi, waht does that mean : Loading device for application Rf_Device from file '' in environment /home/thorsten/Xilinx92i. WARNING:Xst:2677 - Node of sequential type is unconnected in block ....
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15 years ago
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BRAM initialization / bitstream configuration
Hi , The bitstream takes heed of BRAM , so my questions are : * Is it true that all the zeros that we localise in the beginning of configurable part ( of bitstream) correspond to BRAM initialization ?...
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15 years ago
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How program PROM from msc file
---------- Forwarded message ---------- hello !! i have a problem with programming PROM , i must programing it in linux , in windows this programing file is with *.msc extesion , it contans bit file...
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15 years ago
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Using Sysgen v8.2
Hello, I am trying to design a 4-tap FIR filter using system generator for Spartan3 xc3s200-4ft256. But when I try to generate the netlist from Matlab, I get the following error: standard exception:...
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15 years ago
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Xilinx ISE 10 in CentOS not showing in application menu list
Hi, This is my first time install Xilinx ISE in CentOS, I thought it's the free clone of RHEL. But I cannot find the ISE in the application menu list. I don't mean I have to have it, but just don't...
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15 years ago
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Looking for FPGA/CPLD skills to develop prototype
I'm looking for an individual with FPGA/CPLD hardware and software skills to develop prototype of a consumer device. Chicago area preferred. cjt101 at
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15 years ago
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Silicon
Silicon Wafers at PCA supplies silicon wafers for the semiconductor industry. Our products include wafers, thin films and more. We also offer polishing, reclaiming, slicing and lapping of wafers.
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15 years ago
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EDK9.2i simulation problems.
Hi 1) I am having some EDK simulation problems. I am using EDK9.2i with microblaze 7. I have attached a peripheral to the FSL bus using EDK's configure coprocessor and written its corresponding...
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15 years ago
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