Latest threads in Field-Programmable Gate Arraysshow only best voted threads
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About the user defined instruction in APU
Hi, all, I am using ML410 board and EDK 8.2. I am trying to make a PPC system with APU support. I set the UID_1 register according to the rule described in charpter 4 of PowerPC 405 processor block...
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15 years ago
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Yay! We're done with the quadrature encoder!
Aren't we? :-)
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15 years ago
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power supply noise margin
What noise margin should a power distribution network be able to delivery on the 1.2V, 2.5V and 3.3V supply for a Spartan3 ? is +-5% noise budget ok for these supplies ?
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15 years ago
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Need help on ASIC/ASSP FGPA-based prototyping and verification survey
Hi all. I'm running a brief survey on "ASIC/ASSP (FPGA-based) prototyping and verification tools and pratices." If you have experience in this area, I'd appreciate your feedback (see below). Thx! --...
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15 years ago
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xsa-50 issues
hey guys, i have an xsa-50 board by xess. i ran into some issues when trying to test the board using the GXTEST software tool that i downloaded and nothing works. in the past, i used the board and...
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15 years ago
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Programming XCR3064xl - voltage at output stuck at 0
I am programming Xilinx xcr3064xl device: I use the simplest possible code to drive output pins, i.e. I simply assign one or zero, for example: P43
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15 years ago
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value of the weak pull up resistor on IOBs of Virtex5
Hi, Virtex5 datasheet state that there is a optional configurable weak pull-up/pull-down resistor on each IOB. What is the value of that resistor? I looked at the user guide and configuration guide...
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15 years ago
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Is Virtex 4 supported by Jbits ?
Hi ! Is Virtex 4 supported by Jbits ?
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15 years ago
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How to input an analog signal to FPGA board for processing?
Hello, I am a beginer and have a basic question. My project implemented on FPGA board (which is Spartan3E-1600 Microblaze Development Kit) includes ADC and is supposed to do some digital signal...
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15 years ago
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has anyone made PLB_DDR work with 1Gb DRAM chips?
I have a design that consists in part, of the DDR interface from the ML403 board, but with two of these 1Gb DDR parts: instead of these 256Mb parts that were on the original ML403: This should...
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15 years ago
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RLC package parasitics
In the IBIS model i can find the package parasitics R_pkg, L_pkg and C_pkg ... but what does these values represent? is it the total parasitics of the entire pins of the package? is it for single pins...
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15 years ago
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how to set trigger in ChipScopePro for this
Hi all, I have an application where my data refreshes every 10 seconds...It takes so long as I am doing some sort of an averaging over a few million samples and then taking the statistics once in...
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15 years ago
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Xilinx ML507 evaluation board (V5FXT70)?
A past google-search revealed Xilinx employees saying this board will be equipped with a Virtex5/FXT70. From what I remember, the FXT70 requires a full-seat of ISE Foundation 10.x (or the equivalent...
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15 years ago
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getting samples from an RF board onto the system
hi, I have got an RF board (antenna+ADC+Some signal processing boxes on a board). The output is a 2bit data and a clock (16MHz). I need to store this 2 bit data for 1 second onto my system in some...
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15 years ago
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USB full speed final project proposal
I invite you to use free code of a USB full speed project as final work for diploma. The site includes some description of the functionality and main state machines. The code is based on some free...
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15 years ago
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