Latest threads in Field-Programmable Gate Arraysshow only best voted threads
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ISE 10.1 FPGA Editor
I am unable to open a design for read/write editing in FPGA Editor 10.1. Does anyone know if this is the expected result ?
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15 years ago
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Xilinx XCF Flash ROMs - does a datasheet for erase and programming exist?
I would like to erase and program these ROMs from a dedicated interface. Is there any data on how to do this using the JTAG pins? I've found some example code but not a device datasheet outlining the...
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15 years ago
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1250gbps input on virtex-5
Hi, we need to input a continous stream of 32 LVDS data bits at 1.25gbps per pin into a Virtex-5. There is a clock provided for each byte (source synchronous). There was a news item by Xilinx that...
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15 years ago
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problem with microblaze connected ip core
hi, Has anybody written ever an user_logic core for some device which is interfaced to a microblaze? I don't know what's wrong with the following: I used the wizard to generate a simple 8 bit led_port...
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15 years ago
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Every newbie's favorite project: the Quadrature Rotary Encoder revisited
I caught the long thread here on the quadrature rotary encoder from 2 weeks ago. Like the OP in that thread, I am new to combinatorial logic and describing it with VHDL. The problem on the surface...
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15 years ago
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RS232 Interface
Hi I have an evaluation board with a target and a control FPGA. The control FPGA is connected to the target FPGA over 32-bit local bus and can write the data to a host PC over a RS232 interface. Both...
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15 years ago
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timing constraint is impossible to meet
Hi All, When compiling a design I receive the following message: :Pack:1653 - At least one timing constraint is impossible to meet because component delays alone exceed the constraint. A physical...
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15 years ago
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How do I optimize filter coefficient bit length and signal bit length?
Hello all I have made an 8 channel 500kHz low pass IIR-filter in VHDL. The filter uses 32 bits for it's coefficients and 32 bits for it's internal signals. The filter doesn't give the same DC-gain for...
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15 years ago
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Instantiating an lpm dcfifo in Verilog
Hello, I know many will say this is not an appropriate group to post such a question, but I wasn't getting any response on the Verilog group, so please let me apologize. I am new to Verilog and need...
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15 years ago
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synthesis...
hai, I learned from the Xilinx manual that for,while do statements are synthesized in XST.. I would like to know how these statements(for,while,do while) are implemented as logic design(EDIF and...
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15 years ago
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V4 - VTRX & AVCCAUXRX
Hi, DS302 - Pg 11, Table 12, Note 1 says "The maximum VTRX is 1.26V when bypassing the internal AC coupled VICM. VTRX must be less than or equal to AVCCAUXRX". How is VTRX (Termination) related to...
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15 years ago
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bizarre state machine behavior
Hello, I ran into a bizarre state machine problem last week. I had a fairly simple state machine written in VHDL, with an enumerated type and 5 states. The code is of the form : if clock'event and...
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15 years ago
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HELP: a Funny asynchronous input design
input: Asynchronous, non-fix width, non-fix frequeny(but equal or smaller than 30 Mhz), something like random fast signal coming in. System clock is only 40MHz, What can I latch the "rising" edge of...
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15 years ago
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Stratix IV Announced
Altera have put out a press release announcing Stratix IV. Handbook it's gone 40nm and does not appear to have a true 3.3V compatability so buy your shares in manufacurers of bus switches now. John...
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15 years ago
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I cannot find how to map a "record type" in my ucf file.
this is my code: entity Top_Module is port ( o_DSP0 : out MyRecordType ); end Top_Module; whe o_DSP0 is: type MyRecordType is record int4 : std_logic; int5 : std_logic; int6 : std_logic; int7 :...
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15 years ago
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