Latest threads in Field-Programmable Gate Arraysshow only best voted threads
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CRC7 Input bits in Command and Response
Can someone confirm the SDIO CRC7 bits input for the 48 bits command and response and 136 response. For case 1 and 2 the CRC7 is calculated on 40 bits starting from the very first bit - the start bit....
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15 years ago
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Microblaze Cache and FSL problem
Hi all , Out product uses the FSL bus to talk to a co-processor. So far I has the I and d cache for microblaze disabled and the FSL bus was working fine. But as soon as I enable I and d cache I start...
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15 years ago
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Video stream over bluetooth
Dear all, I need to transfer a live video stream from FPGA to let say a PC(Linux) , may you tell the design complexity or how to approach this problem, I have searched a lot and not finding proper way...
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15 years ago
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FPGA Programing file
I intend to build an fpga programer for the spartan fpgas of xilinx I am not sure about the file that i should send over the jtag to program the fpga. I got conflicting information from 2 different...
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15 years ago
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incremental compilation
Hi all, I am experimenting incremental compilation on a design. But the logiclock region assignments are ignored and it doesn't seem to save the compilation time on the second compile. In the first...
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15 years ago
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Xilinx EDK inferred dual port BRAM unconnected clkb
As part of an edk peripheral i have inferred 2 dual port BRAMs which synthesise and simulate correctly For both BRAMs port a is controlled by the microblaze port b is controlled by fsm BRAM 1 is used...
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15 years ago
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it doesn't work if increase a little traffic for DMA read.
The unidirection DMA read only or write only of my PCIE NIC controller V5-based works fine . However,if DMA read(from host--->ethernet port) is progress ,additional i send ping packet continuing from...
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15 years ago
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HWICAP and BRAM
hi all, Iam trying to use HWICAP , as a first test i tried to write to HWICAP BRAM using XHwIcap_StorageBufferWrite and read the stored data using XHwIcap_StorageBufferRead , i noticed that the data...
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15 years ago
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Simple PRNG problem -> clk not recognised as input
Hi I wanted to sythesize a simple PRNG which is implemented as a LFSR. However, the problem is that when I debug the implemnetation on the chip I always get the same random value which are the last...
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15 years ago
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Avalon interconnect fabric : arbiter
Hi all, I just have two simple questions but I can't find the answer from the altera's documents. Each master port has an integer value of transfer shares (M) wich respect to a slave port. A slave...
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15 years ago
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Software instabilities with EDK 10.01 and PPC405?!??!!!
Hi folks, I am short before going mad... I have a Xilinx ML403 board with a Virtex 4 FX12 FPGA sitting on my desk. I use an EDK generated PPC405 design as a submodule. My current task is to interface...
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15 years ago
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URGENT :problem using Ethernet MAC ip core...
hello i am using a virtex 2 pro board to implement a communication system, and want to interface it with my pc (Matlab) via rthernet. for this purpose, i have acquired a Xilinx Ethernet MAC ip core...
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15 years ago
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globals
I need some help with this one... Illegal LOC on IPAD symbol "CLK" or BUFGP symbol "CLK_BUFGP" (output signal=DONE_OBUF), IPAD-IBUFG should only be LOCed to GCLKIOB site. What does that mean ? Thanks
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15 years ago
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asic gate count
Hi, I am looking for some tool / ip that can give me approximate gate count of mapper/demapper. Any helpful hint is greatly welcome. Thanks, Vijayant
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15 years ago
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Extended burst with ADNP with CY7C1386C/CY7C1387C
Hi All, I have to develop a fast data logger in FPGA, which stores the data in CY7C1386C memory. Unfortunately, the author of the board has connected only the ADNP signal, not the ADNC signal. In the...
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15 years ago
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