Latest threads in Field-Programmable Gate Arraysshow only best voted threads

Subject Author Posted Replies
 
FIR filter o/p width
Hai, Is there any formula or general rule to set output width of FIR filter given its input ,coefficients width and number of taps.?? I red in some data sheet of FIR filter deisgn as: output width =...
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Ph.D Student
Good morning. I am currently seeking any publication of my work with FPGA devices, especially for obtaining Ph.D Student. Specifically I've introduced a middleware of communications for FPGA...
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impact / encrypted bitstream
Hi , i tried yesterday to configure my fpga with an encrypted bitstream . Using Impact 10.1 i didn't unerstand the way to do it , i mean how can i enter the key & bit files ? i couldn't find the...
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signal value at power up
Here is my question/issue: say you have: y : out std_logic; signal x: std_logic; you don't assign any value to "x" but you have a condition in your code.. i.e if (x= '1') then y
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Xilinx IO drive level constrain
The IO drive level constrain specifies the drive level of a output signal .. if i am using LVCMOS33 with a drive level of 8mA how can i determine the the output impedance if using f.x a 50ohm...
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Downloading external data file to FPGA
Hi I have a very basic question. Xilinx permits me to initialize Block RAM with an external data file. The thing I am just wondering is, how do I download this file on the FPGA? Do I need to have a...
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Incremental compilation problem
Hi all, I am experimenting incremental compilation following the Quartus II software handbook. But somehow the fitter ignores the logiclock region assignments so it will redo the placement and routing...
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Xilinx XCL woes
OK, so I have this core I wrote which wants to read and write data to an= d = from SDRAM in a Spartan-E3 500 Microblaze system. There will be quite a lot of data moving around, and also I want the...
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How to update a row and a column at the same clock cycle?
Hi I have a simple 4x4 array defined as follows: type rib is array (0 to 3) of std_logic_vector(3 downto 0); signal RanIB : rib; In my combinational logic stage I evaluate a new column that I wanna...
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XILINX core generator question
Hi, Can someone help me please. I am trying familiarize myself with xilinx ISE an d core generator. I was trying to realize simple "fifo core" using core generator. I have done all the procedure and...
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Problem when for program and data memory use SDRAM
I have a PowerPC (Virtex2PRO) and SDRAM (programm and data memory). I anderstand that the bootloader may be use to load programm from systemACE or FLASH Memory. But I whant load programm from...
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using EXP connector of Spartan 3a board
We have just bought a new Spartan 3a 1800a dsp board of Xilinx. We needed i/o pins to control motors and use various sensors and camera. The board contains EXP expansion slots, ( somewhere I found it...
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New Xilinx device package options for S3E & S3A
Thank you XILINX, you list new device package options for Spartan3E: (VQ100 for XC3S500E) and for Spartan3A: (new VQ100 and FT256 options) In the datasheets overview there is a table with device...
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EDK 10.1 Map Error
Hi, Im getting the following error when trying to run the ML505 Standard IP Core Demo project from Xilinx. Im trying with the project that Xilinx gave me,without any modifications....
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XST 3.0 Xess Audio to Ethernet
Im a beginer in VHDL and i got some problems regarding Ethernet usage on XST 3.0 Board. I want to send audio trought ethernet to a second XST 3.0 but i have a lot of problems regarding Ethernet...