Latest threads in Field-Programmable Gate Arraysshow only best voted threads
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HDL tricks for better timing closure in FPGAs
Hi, I am working with FPGAs and trying to take advantage of the parallelism that is available in them. My design is in Verilog HDL and my design is using a lot of resources in the FPGA - ~ 80 % of the...
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15 years ago
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Your favourite DSP textbooks/websites?
hi folks You may have noticed that I've been struggling to explain some rather basic stuff about FIR filters to someone here. I've run out of puff, and wish to sign off by recommending some good...
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15 years ago
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Spartan3 interface with DDR SDRAM
I would like some suggestions on interfacing the Xilinx Spartan3 device with a DDR SDRAM. The idea is to build a controller that will set up the DDR-SDRAM so that I can do a burst read of a page of...
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15 years ago
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Anyone used HiTech global boards?
Hello, I have been using Xilinx MLxxx series boards. For the first time, we are planning to buy a PCIe evaluation board from HiTech global. Do anyone has experience with HiTech global boards before?...
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15 years ago
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FPGA clock frequency
Hai, I am pretty clear about cutoff and sampling frequency of FIR filter. Wat r all the FIR filter constraints to be considered to set FPGA clock frequency before targetting to FPGA device? I guess i...
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15 years ago
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UART master core
Hello, I have 2 boards, of which one has PPC core and other do not. [board1 /w PPC]-------uart-------[board2 /wo PPC] I want to use UART as a debug interface for board2. So,I am looking for a UART...
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15 years ago
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A new FPGA company comes out of Stealth mode - SiliconBlue
Seems there is room for one more ? This seems to push the low-power envelope a little higher in total gates (but still small, compared to the top-end FPGAs). What IS new, is the combination of 65nm...
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15 years ago
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EAPR and EDK 9.1.02i
Hello, In the version of partial reconfiguration tools for ISE 9.1i SP2, Xilinx released several reference designs using the ML403 board which includes a virtex4 FPGA. I tryed to implement the lab3...
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15 years ago
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Xilinx cuts 250 jobs.
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15 years ago
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Compare and update in same clock cycle synthesis problem
Something simular to the following code fragments works in pre-synthesis simulation, but not in real hardware and post P&R timing simulation. entity controller is port ( ... datain in :...
7
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15 years ago
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Xilinx vs Altera
Sorry about the title, everyone put down the flamethrowers, lol. I have a few questions about Xilinx and Altera (actually Spartan-3E versus Cyclone III) which relate to a particular project, so here...
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15 years ago
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Xilinx Fifo Generator Direct Instantiation?
Does anybody know if it is possible to directly instantiate a Xilinx Fifo Generator asynchronous fifo in VHDL? I have a design that requires the use of them, and I think it would be easier to not to...
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15 years ago
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Using ethernet on a Xilnx board (Help appreciated)
First of all let me apologize for any thing of things I"m ignorant about here. Up until very recenty my programming experience was limited to higher level programming language: Python, PHP, Perl, hell...
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15 years ago
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puzzling [and deceiving ?] Actel kit
Hello, I'm sorry for this post but I don't want to rant for nothing, being the optimistic guy that some people know... I have finally got the ProAsic3 kit that I ordered in december. When powered up,...
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15 years ago
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ANNC: ISE WebPACK 10.1i tutorial available
For those that are just getting started with using Xilinx FPGAs, we have released a new version of our ISE/WebPACK tutorial that is updated for version 10.1i: . --...
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15 years ago
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