Latest threads in Field-Programmable Gate Arraysshow only best voted threads

Subject Author Posted Replies
 
Tiny CPUs for Slow Logic
Most of us have implemented small processors for logic operations that don' t need to happen at high speed. Simple CPUs can be built into an FPGA usin g a very small footprint much like the ALU...
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Color sensor with BASYS3 VHDL
Hi, I need to make a circuit which does the following thing: When it sees a red object it will send output 0 until it sees a green objec t (like a well colored cubic toy), after it sees green it will...
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Green/Red detector and button controlled car (BASYS3/VHDL)
Hi, I am a 2nd-year ee student, and I need to make a term Project. With BAS YS3 by using VHDL. My purpose is constructing a car which can be controlled with the buttons o n BASYS3 ( I think I need...
 
Anyone have files from the old Xilinx FTP?
Hi all, Looking for someone who has FTP files from 1997 for the XACT Foundation v6.0.2 update. Web Archive has the files listed here: Anyone capture these files? Thanks.
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Cyclone V decimation
Hi, the input signal is 14 bits signed@750ksps. I would like to decimate it by a modest factor of ~3000. What would be the best way of doing it on a Cyclone V, resource-wise? My usual approach would...
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MachXO2 internal clock tolerance / accuracy
Hi everyone! I have a hard time finding the tolerance / accuracy for the internal oscillator for the MachXO2. I seem to remember it being around 5%, which isn't really that great. Can anyone point me...
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Testing (please ignore)
Please ignore
 
Is it possible to implement Ethernet on bare metal FPGA, Without Use of any Hard or Soft core processor?
Hello folks, Let's say I have Spartan 6 board only and i wanted to implement Ethernet how can it be done? I don't want to connect any Hard or Soft core processor. also I have looked into WIZnet W5300...
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Open Source Synthesis Tools
I know there are some open source simulation tools for Verilog and/or VHDL... I can't recall which or if there are simulators for both languages. I believe there are significant shortcomings in any...
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Xilinx Artix-7 SoM with 8 x GTPs
Hello, I'm looking for a Xilinx Artix-7 SoM (or board..) with at-least 8 x GTP transceivers , preferably 16 , exposed to the connector. Any pointers will be much appreciated. Thanks !
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ARM + FPGA CPU Module running Yocto Linux?
Is there any ARM + FPGA CPU Module running linux using any of: * NXP i.MX6/7/... * Texas Instrument Sitara AM335x or better * Microchip SAMA5 * Renesas RZ/xxx It needs to be connected to a low price...
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Altera Cyclone replacement
Hi, We got an old design with an Altera Cyclone FPGA (EP1C12F324). These are probably obsolete (Can't find any info on them on the Intel site, Farnell is out of stock, etc.). Currently active are the...
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Need help to understand: Efficient Multi-Ported Memories for FPGAs
Hi, I cannot understand the following paper: "Efficient Multi-Ported Memories for FPGAs" FPGA has a structure with 1 write port and 2 read port memory block: 2 memory blocks sharing the same write...
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initializing a small array in Verilog
In my Verilog code I have this line: reg [1:0] ip_list [0:3] = { 2'd2, 2'd1, 2'd0, 2'd1 }; Both Icarus and Vivado seem happy with it and it does what I expect. However, I recently discovered Verilator...
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Can I use Verilog or SystemVerilog to write a state machine with clock gating function?
Hi, Can I use Verilog or SystemVerilog to write a state machine with clock gating function? I know VHDL has no such function and want to know if Verilog or SystemVerilog has the clock gating function...
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