Latest threads in Field-Programmable Gate Arraysshow only best voted threads
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SDRAM controller
I am looking for a SDRAM controller for Xilinx Spartan3 device in Verilog. xapp 134 has one which targets virtex 2 devices. Xilinx MIG can be used for DDR and DDR2 SDRAMs. Can a DDR SDRAM controller...
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15 years ago
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TI DSP + Virtex-5 using EMIF interface
Hi all, I'm working on a realtime application that requires to elaborate a digital video stream 25fps. Algorithms are very time consuming and an hardware parallel solution can help to satisfy time...
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15 years ago
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FPGA reprogrammable? (urgent)
hello.... i wanted to know if fpgas were reprogrammable... if i have a virtex2pro board, use it for a system, and later want to make changes/ additions (hardware), do i lose the already used gates?...
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15 years ago
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Deskew Clock on Synchronous Bus
I am having difficulties in trying to deskew the Clock on a synchronous local bus interface between a Virtex4 FPGA and a PowerPC chip. The instantiation port map of a DCM to provide 0 phase-shift...
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15 years ago
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ANNOUNCE: TimingAnalyzer -- new updated version
Hello All, A new version beta 0.83 is now available. The following changes and additions have occurred. * Improved Image Preview Display. * Context sensitive popup menus to edit objects. * Path set in...
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15 years ago
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Nastat vs.kitkat tuore tutkimus
Transmutaatiotekniikasta. *Maassamme ydinalalla on tuskin mitään niin tarkoin TABU:na pirettyä systeemiä, kuin mahdollisuus neutraloida edes osin maailman vaarallisimpia ihmiskunnan...
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15 years ago
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Aldec Active-HDL and Xilinx/Altera FPGA-vendor library support
I've noticed Modelsim directly compiles the vendor's simulation-libraries from the HDL-source (either VHDL or Verilog.) I simply run the library-generator applet that comes with ISE/EDK. But Aldec...
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15 years ago
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Nutritional yeast
Yksinkertainen kysymys: "Mitä Suomen valtion kansantalous saa tehtyä niillä 100% puhtailla energiamäärillään, joita sille tuottaa esim. wanhasta palaneesta vesiekosähkövoimasta kunnostettu...
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15 years ago
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NIOS-II+LAN91C111
Hi,everyone,I am now doing a work about ALTERA FPGA I use is cycII-60,and the cpu is NIOS-II f,sdram ,lan91c11,dma controller and so on,the main work I should do is to conmunicate the PCs and nios- II...
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15 years ago
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Extracting market feedback from Usenet traffic
I have monitored this group for a while and written a thesis about the possibility to extract market feedback from Usenet traffic. Abstract: Traditional sources of market information are limited in...
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15 years ago
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Re: 1 Pin MTE Cable
"HT-Lab" schrieb im Newsbeitrag news:DTd2k.59$ Hans, look at #1011430 @farnell in UK also availlabe in black, but the farnell number is difficult to find. You can also find the cables in .de: for #...
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15 years ago
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FPGA to FLASH and back?
Hi, I'd like to use an Intel StrataFlash Memory 28F320J3A with my Virtex4 FPGA and write / read data from it. Is there a ready-to-use core available to communicate with the Flash or am I supposed to...
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15 years ago
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length compensation for RocketIO channels
Hi there, I'm designing a PCB that incorporates a Virtex4 FX60 with 16 RocketIOs. All RocketIOs function only as a receiver and I wonder if you should care for length compensation on my FR4 board,...
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15 years ago
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ANNOUNCE: SiliconBlue Pioneers New FPGA Technology for Handheld, Ultra-Low Power Applications
SiliconBlue Pioneers New FPGA Technology for Handheld, Ultra-Low Power Applications Monday, SiliconBlue(tm) announced a revolutionary new class of single-chip, ultra low-power FPGA devices that set a...
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15 years ago
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Re: ANNOUNCE:-- TimingAnalyzer Free Version -- Draw timing diagrams
Have you ever met Tux? :) -- % Randy Yates % "Maybe one day I'll feel her cold embrace, %% Fuquay-Varina, NC % and kiss her interface, %%% 919-577-9882 % til then, I'll leave her alone." %%%% % 'Yours...
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15 years ago
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