Latest threads in Field-Programmable Gate Arraysshow only best voted threads
| Subject | Author | Posted | Replies | |
|---|---|---|---|---|
|
|
FPGA IO Pin Unwanted Coupling
Hello, I am fairly new to FPGA design and have a Xilinx Spartan 3 board, that has a 50 pin IO bank. When I load up a design, and route signals to different parts of this IO region, some of the signals...
2
|
15 years ago
|
2 | |
|
|
Simulate Microblaze in System Generator
Hi. I've spent hours trying to find a simple example/turorial of a microblaze imorted into system generater for simulation. All i find is HW co-sim examples. Is there a tutorial out there that does...
—
|
15 years ago
|
— | |
|
|
Old Mits Dram Datasheet Search
Hi- I'm trying to locate the data sheet for an old 1M x 1 Mitsubishi dram part: MSM41000BJ (70nS) An internet search is coming up empty. If you can help out it would be appreciated. Thanks Jim
1
|
15 years ago
|
1 | |
|
|
CPLD beginner questions
I'm currently using GALs (16V8-18V8-22V10), but my current board requires 4 GALs and I would like to replace them with one CPLD which would also replace 4 other general ICs. I've never had the guts to...
9
|
15 years ago
|
9 | |
|
|
export to project naigator
I am running some xmp file provided by the manufacturer. The flow for generating bit file was smooth using 7.1 and 8.1 versions of ISE/XPS. I used to generate a netlist using xps. then run export to...
1
|
15 years ago
|
1 | |
|
|
Automotive Temperature +100 deg C+ FPGA's -- who's parts are available from stock
Automotive Temperature +100 deg C+ FPGA's -- who's parts are available from Distributor stock? Am really interested in -40 to +125 deg C solutions that are Automotive grade or Similar --
2
|
15 years ago
|
2 | |
|
|
chipscope analyzer error
I get the following error with chipscope analyzer whenever I do the intialize chain. ERROR: Socket Open Failed. localhost/127.0.0.1:50001 localhost Connection refused ERROR: Failed to detect cable....
6
|
15 years ago
|
6 | |
|
|
Xilinx EDK - LibGen Error!!!
hi all.... i use xilinx EDK 9.1i. i'm trying to use opb EMAC.... when i run libgen i get this error: "Running system level Update ... Running UPDATE Tcl procedures for OPTION SYSLEVEL_UPDATE_PROC......
—
|
15 years ago
|
— | |
|
|
Link for Joining the FPGA/CPLD Design Group on LinkedIn
Link for Joining the FPGA/CPLD Design Group on LinkedIn Login to LinkedIn to keep in touch with people you know, share ideas, and build your career.
—
|
15 years ago
|
— | |
|
|
PLB master : Split bus architecture
Hi, There are three sources for plb master interface. 1) plb_master_single.vhd and plb_master_burst.vhd use a combined read- write controller for the qualifier signals. 2) plb_master.vhd has a split...
—
|
15 years ago
|
— | |
|
|
DISABLING POWERPC IN VIRTEXII PRO
I have AMIRIX ap1070 board with a xilinx virtex II PRO XC2VP70 . I am trying to use it for network based application . I am not using the powerpc at all and was wondering if there is a way to disable...
2
|
15 years ago
|
2 | |
|
|
New Home
Hi, Well, since the Xilinx functional re-organization, I have a new responsibility (here at Xilinx). The bad news(?): I will still participate here on c.a.f. and my Xilinx blog (is that of any use to...
3
|
15 years ago
|
3 | |
|
|
FPGA to solve the two most annoying problems on usenet - Suggestions Welcome
As you all know, downloading files from usenet leaves you with two sets of files.. The rar files from what you're downloading and the par2 files for incomplete file repair. If anyone has attempted to...
13
|
15 years ago
|
13 | |
|
|
Ryhmän sfnet.tori.veneily virallinen kuvaus
*Yleisön pyynnöstä alan julkaisemaan Suomen ydinaavikoitumisen nykytilastamme kertovaa faktaa. M.T.05.05-08. Ilmatieteen laitos. PAIKKA SADE mm. _________________ Helsinki Kiikkala Turku 0,2mm...
—
|
15 years ago
|
— | |
|
|
Dram Refresh Controller Tutorial wanted
Hi... I have a desire to interface some dram to a project and was internet searching for some in depth tutorials on refresh controllers, but haven't found anything that I am happy with. Does anyone...
1
|
15 years ago
|
1 |