Latest threads in Field-Programmable Gate Arraysshow only best voted threads
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DDR2 termination
Hi, After reading over the documentation for DDR2 and the SSTL signalling standard, I have a question about the role of termination in DDR2. It appears to me that in addition to the usual termination...
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15 years ago
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beginner
Xilinx Spartan 3E starter kit. process (boff, bon ) begin if (boff= '1') then led
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15 years ago
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altera technical question?
hi all: I have a question about stratix II .An oscillator must drive a constant clock frequency to an FPGA pin. The maximum frequency limit depends on the speed grade of the FPGA. Frequencies of 50...
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15 years ago
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FPGA JTAG commands
Hi, I am trying to access a QuickLogic FPGA via JTAG. I am using a FTDI DLP2232M-G (and associated FTCJTAG api) to connect to the device. So far I have been able to read and write data to the device...
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15 years ago
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DMA_BURST_SIZE in Xilinx EDK 9.1i
Hi, i have generated a user ip with dma/sg support. now i want to disable the dma burst transfer. -- specify the size (must be power of 2) of burst that dma uses to -- tranfer data on the bus, a value...
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15 years ago
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VHDL refactoring tools
Greetings All, I've just spent 20 mins editing 12 VHDL files to add two signals and route them up and down a design hierarchy. Tedious and not exactly rocket science. Is anyone aware of any...
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15 years ago
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Error while doing 'Generate Netlist' in xilinx 9.2i
Hi all, When I do Generate Netlist in Xilinx 9.2i, I get the following error - ------------------------- ./ line 2: $' ': command not found ./ line 4: $' ': command not found ./ line 6: $' ': command...
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15 years ago
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Synplify beeping
I am running Synplify from the Lattice ispLever tools and every time I compile the design Synplify beeps when it is started and beeps when it finishes. It is a lot louder than the other sounds the...
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15 years ago
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which commercial HDL-Simulator for FPGA?
As commodity PC hardware and prouctivity applications deline in price, EDA tools are as (relatively) expensive as ever, necessitating yet another discussion of "Which simulator is right for me?" The...
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15 years ago
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NVIDIA’s Tesla T10P Blurs Some Lines
What do you guys think about that?: I heard about Cuda and GPU acceleration for HPC applications before but this time I feel (like the author Kevin Morris) that this solution is getting traction. I...
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15 years ago
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Question about coefficient padding
Hi, In the document of FIR Complier v3.2, it talks about coefficient padding. I have several questions about that topic. It gives an example: MAC0 l m n p MAC1 h i j k MAC2 d e f g MAC3 0 a b c It...
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15 years ago
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Stratix II GX EP2SGX90FF1508C3N
I also have 34 pieces of the Stratix II GX, the part number is EP2SGX90FF1508C3N Best Regards, Jon E. Hansen (949)864-7745
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15 years ago
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Mapping the DCM clock output onto a global buffer
Hello, I am using a Xilinx Spartan-3 FPGA (XC3S200-4), and I am having difficulty mapping the Digital Clock Manager (DCM) output onto my clock net using a global buffer. My intent is to take my...
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15 years ago
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Precision Synthesis verilog netlist black box question
Hey, Just wondering if anyone knows the command to stop module declarations of black boxes being written out to the verilog netlist precision generates for post-synthesis simulation. At the moment i'm...
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15 years ago
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MIG core generator problem
Hi, I have one question about Memory Interface Generator. This problem I can't solve for a period of time so I decided to ask help. The thing is this. I generate my Mig core from the project. THis...
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15 years ago
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