Latest threads in Field-Programmable Gate Arraysshow only best voted threads

Subject Author Posted Replies
 
Linked Group for FPGAs & CPLDs
Hi, There is a new FPGA Linked in Group. Joining will allow you to find and contact other FPGA, CPLD members on LinkedIn. The goal of this group is to help members: -> Reach other members of FPGA &...
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Xilinx and RAM/ROM monitoring
Hi, I was wondering if a tool exists to monitor the content of a RAM, ROM connected to a Xilinx FPGA. I would like to be able to control the content of those memories like a debugging tool for...
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Xilinx SecureIP simulation and third-party simulators?
Starting with ISE 10.1, has begun migrating some hard-IP simulation models from Smartmodel to "SecureIP." For now, the SecureIP blocks can only be simulated in 1 simulator: Modelsim 6.3c (or later) "...
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DC-Fifo with write pointer confirm/clear
Hi, I have designed a VHDL single clock FIFO with write pointer that can either be confirmed or cleared that is the read side of the fifo does see the write counters only when these have been...
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FPGA based database searching
Hello, I've been searching the internet for days now and still I'm not sure about what I am trying to do. Okay now, I've got a software implementation in ANSI-C for a complex database searching. The...
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Cellular automata on a S3E SK
Hi group, Another video by me to showcase another application I made. Just to show can be done with a Spartan 3E Starter Kit, creativity and some free time. Don't be afraid to ask for code ;) Enjoy!...
 
is lwIP absolutely necessary for tcp-ip?
hello. i am trying to set up ethernet interface between my pc and a XUP Virtex2Pro board, and want to use tcp/ip. xilinx edk seems to have the lwip stack as a library. is it necessary to use this...
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ANNOUNCE: new version TimingAnalyzer beta0.84 available
Hello All, A new version beta 0.84 is now available. The following changes and additions have occurred. 1. Added eps,pdf,svg,png,gif,and emf file formats to SE 2. Added bus value button so H L Z and X...
 
ANNOUNCE: new version beta0.84 available
Hello All, A new version beta 0.84 is now available. The following changes and additions have occurred. 1. Added eps,pdf,svg,png,gif,and emf file formats to SE 2. Added bus value button so H L Z and X...
 
virtex-5: can't use DCM (too low input frequency)
Hi all, I have a camera and a Virtex-5 FPGA, and i would like to store frames in FPGA Block Ram. In my design (that worked with Spartan-3E) i need to double camera clock frequency, in order to get all...
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Image Sensor Interface.
Hi, I am planning to read an image sensor using an FPGA but I am a little confused about a bunch of things. Hopefully someone here can help me understand the following things: Note: The image sensor...
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Newbie Verilog Question / ModelSim
Hi, I am thinking of using Verilog for a project I am working on. Originally I was going to use a processor core (and C) on an environment someone set up for me in VHDL/Verilog, then I thought of...
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Altera, Cyclone III, PCI, LVCMOS, & 3.3V
Quick summary: Under what circumstances, if any, can you use 3.3V VCCIO for PCI, with Cyclone 3 parts ? I've read Altera apnote AN447 I understand this apnote to suggest that any/all 3.3V LVTTL or...
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help using lwIP with xilinx EMAC
hello... in order to interface between my pc (via matlab) and the XUP Virtex 2 pro board, i came to know i'll have to use the lwIP library/stack... is that right? (there is no OS running on the ppc405...
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virtex 5 security / embedded key memory
Hi , i would like to know which kind of memory that Xilinx use for the encryption key storage ( virtex 5 ) , is it an asic ? Also , is it possible to know the features of the dercrypter ( type , speed...
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