Latest threads in Field-Programmable Gate Arraysshow only best voted threads
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Board for Hardware in loop
I am looking for fpga-dsp-board with USB Interface for hardware-in- loop. I don't think I want to mess with USB. I just want to use some easy to use board which will allow me to transfer data (at high...
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15 years ago
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VHDL libraries
I am working with a processor core that is written in VHDL and relies on a BUNCH of IP vendor provided libraries. I was able to build all the required libraries in ActiveHDL and compile the top-level...
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15 years ago
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Type Casting in verilog
I just wanted to know whether type casting in verilog is sythesizable or not?
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15 years ago
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Translate problem
when i try to translate it, it tells me this ERROR:NgdBuild:753 - "top.ucf" Line 4: Could not find instance(s) 'DCM_SP_INST' in the design. To suppress this error specify the correct instance name or...
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15 years ago
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Design of a BFSK transmitter/receiver using Xilinx System Generator
I would like someone to comment my BFSK design as I am a student and not much experienced.
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15 years ago
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What is TIEOFF_X0Y31
Hi, I ran into a problem which is related to TIEOFF_X0Y31. I opened FPGA_Editor and see such sites around Xilinx Virtex5. i am wondering what's this site for? I googled and could not get any infos....
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15 years ago
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on FRAME_ECC_VIRTEX4 functionality
Hi all, I have two questions: 1.- On the meaning of the syndrome word: Virtex-4 Libraries Guide for HDL Designs says that syndrome(11) = 0 means there is a one bit error and that syndrome(10 downto 0)...
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15 years ago
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EDK question
Hi everybody, I am using PPC to configure number of LUTs using HWICAP, my question is , Is it possible to generate an interrupt internally according to a change in register value , as i want to do new...
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15 years ago
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lwip for FPGA
Hi, I am new to using lwip. I am wondering if you can advice me on the same. I need to transfer data from PC to Microblaze microprocessor on a Xilinx FPGA board and vice versa as fast as possible. i...
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15 years ago
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FIR filter with integer coefficients
Hai, Can i implement FIR filter in FPGA using fixed point number.. I referred various FIR filter implementation in FPGA all have used integer coefficients for their implementation and i am interested...
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15 years ago
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I-map Websolution...turning possibility into reality...
I-Map Websolutions: web hosting Philippines - Web Hosting Provider Today=92s modern world we have lots of changes, new ideas created to explore, develop, enhance especially in corporate world that=92s...
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15 years ago
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Quartus-II 8.0 resource-sharing? (why inferred addsub takes 2x LUTs?)
I created a simple Verilog-2001 test-module: `default_nettype none module top #( parameter integer D_W = 16 ) ( input wire sel, input wire signed [D_W-1:0] ina, inb, output wire signed [D_W:0] out );...
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15 years ago
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ANNOUNCE: TimingAnalyzer version beta 0.85
Hello All, A new version beta 0.85 is now available. The following changes and additions have occurred. 1 Quickly add previously used Delays and Constraints from pop-up menu 2 The current state is...
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15 years ago
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arithmetic problem
Hi, the following code : library IEEE; use use ...
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15 years ago
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EDK DMA peripherals?
Hi, I am using an EDK-generated PPC subsystem on a ML403. I wonder if it would be complicated to create a peripheral that has high speed master access to the SDRAM. I would like to build a shared...
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15 years ago
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