Latest threads in Field-Programmable Gate Arraysshow only best voted threads
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Constraints for router
Hi, I need to ensure that two FFs are placed close to each other. Does anybody know if it's possible? Can I use any constraints in my UCF, or any attributes of signals? Thanks
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15 years ago
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OPB_CENTRAL_DMA
Has anybody used central_dma to copy data between peripherals and processors, or between two buffers in bram mermory. I have added it to the design and configure but, I receive a DMA BUS TIMEOUT. Best...
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15 years ago
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Have you ever experimented some problem with External Memory?
Hello, I ask for people who has detected some problem in programs running in External Memory (Micron DDR SDRAM). These problems are about "printf" and "malloc" functions, and the results are...
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15 years ago
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Processor Debug interface
Hi all, I wanted to know about the different debug interfaces used(or standards present like JTAG etc...) in a wireless SOC having a RISC processor. ARM uses some thing called trace debugging, I...
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15 years ago
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C problem
hi all, I am using PPC to make runtime configuration to certain luts in EDK , my problem is i created my own C function , and i want to use my c function in many designs so, i created header file...
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15 years ago
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Insert IP cores
Im trying to make use of the fifo in my Spartan3E starter kit i've added the component declaration and instantiation template as instructed in the vho file. but im getting the following error when i...
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15 years ago
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Spartan3: INIT_B doesn't go LOW after PROG_B goes LOW in 2% of cases
Hi All, I have a big system which uses more than 1000 Spartan3 FPGAs. The chips are configured either remotely via a dedicated communication interface, or downloaded automatically from FLASH by simple...
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15 years ago
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synthesis in xilinx
hai, I understood that the design synthesized in one device of xilinx can be implemented in the other device.. but whether the design synthesized from other tools like celoxica compiler for one xilinx...
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15 years ago
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connecting fpga to TI emif
Hi, I have a Lyrtech SFFSDR board, where a virtex4 SX35 is connected to the emif of a davinci dm6446. I woul like to create a very basic register accessible for reading and writing from the davinci. I...
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15 years ago
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minipci breadboard with fpga
Hi, I'm looking for a minipci card with an FPGA in order to work for some project. The PCI interface should be programmed inside the FPGA apart from other application specific functions. Unfortunately...
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15 years ago
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Timing Analyzer report for IOBs -- 1GSPS DAC interface
Hi, I'm designing a 1GSPS DAC interface that sends a 500MHz clock and 16bit DDR parallel data in Virtex-5 xc5vlx95t-1ff1136 device. The 500MHz input clock is driven to a BUFIO that connects to the CLK...
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15 years ago
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real time FIR implementation in FPGA
hai, I have stored my filter coefficients in FPGA.I have not stored my input samples it will directly given to the FPGA FPGA logic will wait for new input samples,accepts it,process it and then wait...
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15 years ago
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VHDL code for RCOM message
Hi, I am presently writing Testcases and Test benches for my Communication control modules which are used in Boeing spoilers. I need the code for checking (validate and verify) a Message format of my...
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15 years ago
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How do I program an fpga once it has been designed and layout is complete
Trying to design an FPGA from scratch, but not sure how this fpga should be programmed. It is going to be a tile concept fpga with a LUT SRAM architecture. I have the resources to write VHDL/Verilog,...
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15 years ago
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Nintendo DS Screenshots / Video Capture
Hi All, I'm starting to look at building something that will allow me to take screenshots and do video capture of both of the Nintendo DS screens. Amazingly there is actually nothing available that...
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15 years ago
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