Latest threads in Field-Programmable Gate Arraysshow only best voted threads

Subject Author Posted Replies
 
How do big compagnies use Verilog/VHDL for processor designs?
I have a question on how big companies like Intel/AMD use VHDL and Verilog internally for their processors. For example, if they implement an ALU. Do they implement the ALU on an RTL-level or do they...
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HOW TO READ A 64 BIT REGISTER IN 2 CLOCK CYCLES IN VERILOG
There is a 64bit input that is stored in register. A single clock cycle can read 32bits at a time. For implementing this 4x1 mux is used as 32bit imag e is divided into 8bit. The problem I'm facing is...
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Unique uses for the DSP48
I've tried to figure out how to use the Xilinx DSP48s for Galois arithmetic , but they really aren't that useful for that. The new ones can do a 96-bi t unary XOR, which can be used for GF(2) matrix...
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Microchip UNI/O controller core for FPGA
Hi, I needed to access the Microchip 11AA02E48 EEPROM located on a FPGA board. Unfortunately, I couldn't find any VHDL/Verilog sources of a UNI/O controll er. Therefore, I have decided to write my...
 
bare-metal ZYNQ
Assume I'm a pointy-haired boss trying to help one of my guys. I think that... The Xilinx ZYNQ (FPGA+ARM on a chip) has a hard boot loader. It figures out what the boot device is (serial flash, SD...
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Nallatech BenBlue-II software
Hello folks, I try to use an old FPGA card from Nallatech, it is a BenNuey PCI card. I have the FUSE software, but I am missing the CD for the DIME card named BenBlue-II and Nallatech, unfortunately,...
 
Problem in ADV7611 with Interlace Input
Hello folks, We are developing demo Aplication for HDMI input and output. for this we are using PicoZed 7030 board with FMC HDMI daughter card. the daughter card consist of Adv7611 as HDMI receiver...
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FIFO timing, the right way
Hi all, I am working on a block that needs to accumulate (at least) K data items and then consume them in a burst, while the next group of items might be flowing in. As the items are not consumed...
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Up/Down Binary Counter with Dynamic Count-to Flag
hello, i need to solve this problem in verilog:Up/Down Binary Counter with Dynamic Count-to Flag this is start cod: module DW03_bictr_dcnto_inst( inst_data, inst_count_to, inst_up_dn, inst_load,...
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FPGA board on ebay
If anyone is interested I just got round to putting up a nexys Video artix-7 board on ebay. This is a private not trade sale. VctIxm Feel free to contact me if you have questions but it pretty much...
 
BITSLIP STATE MACHINE
Hi, I am trying to design a state machine for bitslip function but simulations dont seem to be correct. I cant figure out where the bug is. here is the code and test bench. module bitsliplogic( CLOCK,...
 
Replaceme EPROM by CPLD/FPGA
We have a product that includes a small parallel OTP memory. These devices get very hard to get and no easy alternative is available that fits in the very small available space. A PLCC32 EPROM will...
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TCS34725 Basys3 VHDL
Hi I am trying to use TCS34725 to identify Green and Red Colors, it has I2C interface and i could not find any I2C interface about this and i am not capable to write a protocol code what should I do I...
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High-level synthesis
It's been about 3 years since I've done any *serious* FPGA work. I used mostly VHDL or sometimes my own Matlab scripts to create automated VHDL files. I would like to know if anyone has used...
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Xilinx M1 Pad file
Is there anyone that has a description of the Xilinx M1 Pad file syntax? An example file would do as well. Best Regards AP