Field-Programmable Gate Arrays - Main Page

Do you have a question? Post it now! No Registration Necessary

Field-Programmable Gate Arrays - FPGAs, PLDs and other programmable logic ICs are discussed here
Web, RSS and Social Media interface to comp.arch.fpga
There are 83196 individual articles here that are part of 15188 discussions
Please see below the list of the most recent and the best rated articles in Field-Programmable Gate Arrays

The most recent discussions

Division Algorithms

January 16, 2021, 9:31 pm

I am looking for an algorithm to calculate a floating point divide. There a re a number of options, but the one that is most clear to me and easiest to implement on the hardware I am designing see... Read more »

Achronix Semiconductor in Talks for Merger

  [ 2 ]
January 6, 2021, 6:35 pm

An IPO of sorts really. They would merge with ACE Convergence Acquisition Corp NASDAQ: ACEV and this company would be seeking investors. Achronix has been profitable, so this should be a good dea... Read more »

Fixed Point Arithmetic

December 29, 2020, 8:25 pm

I don't know why I thought it would be easy. The arithmetic is not so hard by itself. But changing all the equations to normalize the variables is n ot so easy. Then there is the issue of needi... Read more »

PHB FPGA question

December 27, 2020, 8:50 pm

OK, pointy-haired boss question. Given a ZYNQ 7020, speed grade 1. A 3.3 volt i/o bank gets a clock from an LVDS input. We have a resync flop in an i/o cell, clocked by this, with a D input from s... Read more »

Temperature Sensor Error

December 16, 2020, 5:29 pm

Hi everyone, I'm trying to implement the following code on the NEXYS A7 board and it seems the I2C communication isn't working properly. Read more »


December 12, 2020, 9:36 pm

I had a newbie working on a bit wise CRC32 implementation and he could not get the results of any of the many online CRC32 generators available. So I coded up the same algorithm and tried it mys... Read more »

Gowin - This Just Got Real

December 9, 2020, 6:09 pm

I've been watching the various FPGA startup companies and a couple have pro duct available through mainstream distributors. The one I like the most is Gowin because of the easy to use packages th... Read more »

Why am I getting different results with two files collapsed into one?

December 6, 2020, 5:27 am

[code] // (c) 2020 Kevin Simonson module equ2 ( output result , input leftOp , input rightOp); wire notRight, xorWeak; supply1 power; supply0 ground; nmos #(3) nRg( notRight, gro... Read more »

Synthesizable open FPGA cores

November 28, 2020, 6:11 pm

Hi Experts, I am looking for Synthesizable FPGA (Xilinx) SOC cores like RUSC-V etc ( more than 100K LUTs) for evaluating their timing performance. Could you please point me to their repositories... Read more »

To Reset or not to Reset, That is the Question!

November 24, 2020, 5:25 am

Whether tis nobler to suffer the slings and arrows of outrageous judgement or just add the pointless, incorrectly working async reset that every frigg in' text book and every training example show... Read more »

Click here for other recent discussions »

The best rated discussions


Microchip UNI/O controller core for FPGA

Hi, I needed to access the Microchip 11AA02E48 EEPROM located on a FPGA board. Unfortunately, I couldn't find any VHDL/Verilog sources of a UNI/O controll er. Therefore, I have decided to writ... Read more »


Lowest Power Design in an FPGA

What is the lowest power design you have done in an FPGA or CPLD? There have been some very low power devices on the market for a number of years now. I assume there have been some designs that... Read more »


VHDL BFMs and VVCs for AXI4-Lite, Avalon-MM, UART, I2C and SPI - for free ...

UVVM - the new VHDL verification methodology is a very good way to structur e your VHDL testbenches - and to make easily understandable, maintainable, extendible and reusable testbench architectur... Read more »


Software for FPGA-based PC scope

Hello, Although I am a newbie in FPGA design and have experience only with some simple designs so far, I am thinking of some more ambitious project and want to design a FPGA-based PC scope working in... Read more »


lowest-cost FPGA and CPLD

I heard that Lattice Semiconductor Corporation boasted they were providing the lowest-cost FPGA and CPLD solutions, not sure if the news was true. Could anybody confirm it? If so could anybody give m... Read more »


ICTP Open Hardware Initiative – Invitation to part icipate in an open-surve...

Dear Colleagues / Friends We would like to invite you to participate in an important survey regarding an open FPGA Hardware initiative by the International Center for Theoretical Physics (ICTP - UN... Read more »


Call for beta users for Sigasi integration with Altera Quartus

Hi everybody, I am Philippe Faes, founder of Sigasi. Sigasi sells a design entry and code comprehension tool for VHDL. Many users of Altera Quartus have asked us if Sigasi plugs in to Quartus. We hav... Read more »


Job - Promotion - 2D/3D Bildverarbeitug - FPGA

Stellenausschreibung - Echtzeit-2D/3D Bildverarbeitung ------------------------------------------------------ Verg. Gr. 13 TV-L zu besetzen. Schwerpunkt der Forschungsarbeiten liegt auf dem folge... Read more »