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There are 83216 individual articles here that are part of 15195 discussions
Please see below the list of the most recent and the best rated articles in Field-Programmable Gate Arrays

The most recent discussions

A bewildering Visio-2019 problem!


April 11, 2021, 6:09 pm

Unfortunately, I met a bewildering problem with Visio-2019. I have been using Visio-2019 to make circuit drawings, everything goes well until yesterday. I modified a drawing, and generated a PDF f... Read more »

Research Assistantship (Fall, 2021) at Dept. of Computer Engineering, Hally...


April 5, 2021, 5:14 am

Research Assistantship (Fall, 2021) at the Graduate School, Dept. of Comput er Engineering, Hallym University, Korea The [AI Accelerator Design Lab] of the Hallym University seek to recruit pr omi... Read more »

Hi can anyone please tell me how to rectify this error


March 14, 2021, 4:55 pm

Hi can anyone please tell me how to rectify this error ERROR:MapLib:30 - LOC constraint J17 on topsegF is invalid: No such site on the device. To bypass this error set the environment variable '... Read more »

MachXO2 pin mismatch error


March 11, 2021, 1:33 pm

Hi, I am trying to use a PMI ROM memory block in Lattice Diamond/VHDL: decoder_rom0 : pmi_rom generic map ( pmi_addr_width => 3, pmi_data_width => decoder_rom_data'length, pmi_re... Read more »

Fully Comitted to LVDS as Comparitors


February 23, 2021, 1:05 am

I working on a design where there will be some five sigma-delta ADCs and several specific level detect inputs each using an LVDS input pair as a comparator. So I'm pretty committed to this working. ... Read more »

Achronix?


January 29, 2021, 2:00 am

Has anyone used Achronix FPGAs? Read more »

Communist Chinese Military Companies


January 23, 2021, 7:06 pm

A new FPGA company in China has appeared on a list of Communist Chinese Mil itary Companies (CCMCs). One article I read says this does not mean they ar e on the US military end user list (MEU) or t... Read more »

Division Algorithms


January 16, 2021, 9:31 pm

I am looking for an algorithm to calculate a floating point divide. There a re a number of options, but the one that is most clear to me and easiest to implement on the hardware I am designing see... Read more »

Achronix Semiconductor in Talks for Merger

  [ 2 ]
January 6, 2021, 6:35 pm

An IPO of sorts really. They would merge with ACE Convergence Acquisition Corp NASDAQ: ACEV and this company would be seeking investors. Achronix has been profitable, so this should be a good dea... Read more »

Fixed Point Arithmetic


December 29, 2020, 8:25 pm

I don't know why I thought it would be easy. The arithmetic is not so hard by itself. But changing all the equations to normalize the variables is n ot so easy. Then there is the issue of needi... Read more »

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The best rated discussions

rating
5

Microchip UNI/O controller core for FPGA


Hi, I needed to access the Microchip 11AA02E48 EEPROM located on a FPGA board. Unfortunately, I couldn't find any VHDL/Verilog sources of a UNI/O controll er. Therefore, I have decided to writ... Read more »

rating
5

Lowest Power Design in an FPGA


What is the lowest power design you have done in an FPGA or CPLD? There have been some very low power devices on the market for a number of years now. I assume there have been some designs that... Read more »

rating
5

VHDL BFMs and VVCs for AXI4-Lite, Avalon-MM, UART, I2C and SPI - for free ...


UVVM - the new VHDL verification methodology is a very good way to structur e your VHDL testbenches - and to make easily understandable, maintainable, extendible and reusable testbench architectur... Read more »

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5

Software for FPGA-based PC scope


Hello, Although I am a newbie in FPGA design and have experience only with some simple designs so far, I am thinking of some more ambitious project and want to design a FPGA-based PC scope working in... Read more »

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5

lowest-cost FPGA and CPLD


I heard that Lattice Semiconductor Corporation boasted they were providing the lowest-cost FPGA and CPLD solutions, not sure if the news was true. Could anybody confirm it? If so could anybody give m... Read more »

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5

ICTP Open Hardware Initiative – Invitation to part icipate in an open-surve...


Dear Colleagues / Friends We would like to invite you to participate in an important survey regarding an open FPGA Hardware initiative by the International Center for Theoretical Physics (ICTP - UN... Read more »

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5

Call for beta users for Sigasi integration with Altera Quartus


Hi everybody, I am Philippe Faes, founder of Sigasi. Sigasi sells a design entry and code comprehension tool for VHDL. Many users of Altera Quartus have asked us if Sigasi plugs in to Quartus. We hav... Read more »

rating
4

Job - Promotion - 2D/3D Bildverarbeitug - FPGA


Stellenausschreibung - Echtzeit-2D/3D Bildverarbeitung ------------------------------------------------------ Verg. Gr. 13 TV-L zu besetzen. Schwerpunkt der Forschungsarbeiten liegt auf dem folge... Read more »