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Please see below the list of the most recent and the best rated articles in Field-Programmable Gate Arrays

The most recent discussions

Verilog HDL Finite State Machine - detecting a decimal number

November 7, 2021, 4:58 am

Hi all, I am trying to build a sequence detector to detect a decimal number like 10 92 when a stream of numbers from 0-9 is given as input. Do you think just c hanging the width of input i.e paral... Read more »

Quartus II Synthesis - System Memory Issues for Large Stratix 10 Design

October 29, 2021, 5:21 pm

Hello, I have a Stratix 10 design that is based around an ip core generated using Intel's HLS. The core does some simple floating point operations and by its elf uses very few resources (1 DSP, a... Read more »

UDP -FPGA point to point

October 18, 2021, 12:59 pm

Hello everyone, I have recently started working on a project using Ethernet in an FPGA and I am using the UDP protocol for communication between the PC and the FPGA. The communication is happening p... Read more »

Xilinx forums have disappeared?

September 26, 2021, 9:00 pm

Today I tried to find certain old post on the Xilinx forum. Goggle has found it in their database, but the link leads to nowhere and is finally redirected to . There i... Read more »

Is there any software I can use to transform state machines in VHDL into dr...

September 8, 2021, 8:24 pm

Hi, I have designed many state machines in VHDL, and I hope to use any software to transform the state machines in VHDL into drawings. Is there any software I can use to transform state machines in... Read more »

GDB from my university...

August 15, 2021, 7:17 pm

CS302 ? Digital Logic Design Graded Discussion Board You are required to program a PAL device to design a 64-bit counter. The st ated PAL can be programmed using ABEL (Advanced Boolean Expression ... Read more »

PLL dynamic phase shift

August 1, 2021, 5:02 pm

Why ck_dynamic is having period of 0.822ns when it is stated to be of 333MHz frequency? Read more »

A state machine design problem

July 8, 2021, 2:56 pm

Hi, I have the following VHDL code for a state machine: type Output_State_t is ( State_a, State_b, State_c); signal Output_State, Output_State_NS : Output_State_t ; At a clocked process, there... Read more »

Synthesis : Pan's Algorithm

July 8, 2021, 1:25 pm

Have anyone studied Pan's Algorithm previously ? 1. How is Pan's algorithm being... Read more »

Why Xilinx Ten Gigabit Ethernet PCS/PMA IP Core 32-bit version use less res...

July 3, 2021, 4:43 am

The 32-bit version should have better latency performance but I think it's more complex, so it should use more resources. But as the link below Read more »

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The best rated discussions


Microchip UNI/O controller core for FPGA

Hi, I needed to access the Microchip 11AA02E48 EEPROM located on a FPGA board. Unfortunately, I couldn't find any VHDL/Verilog sources of a UNI/O controll er. Therefore, I have decided to writ... Read more »


Lowest Power Design in an FPGA

What is the lowest power design you have done in an FPGA or CPLD? There have been some very low power devices on the market for a number of years now. I assume there have been some designs that... Read more »


VHDL BFMs and VVCs for AXI4-Lite, Avalon-MM, UART, I2C and SPI - for free ...

UVVM - the new VHDL verification methodology is a very good way to structur e your VHDL testbenches - and to make easily understandable, maintainable, extendible and reusable testbench architectur... Read more »


Software for FPGA-based PC scope

Hello, Although I am a newbie in FPGA design and have experience only with some simple designs so far, I am thinking of some more ambitious project and want to design a FPGA-based PC scope working in... Read more »


lowest-cost FPGA and CPLD

I heard that Lattice Semiconductor Corporation boasted they were providing the lowest-cost FPGA and CPLD solutions, not sure if the news was true. Could anybody confirm it? If so could anybody give m... Read more »


ICTP Open Hardware Initiative – Invitation to part icipate in an open-surve...

Dear Colleagues / Friends We would like to invite you to participate in an important survey regarding an open FPGA Hardware initiative by the International Center for Theoretical Physics (ICTP - UN... Read more »


Call for beta users for Sigasi integration with Altera Quartus

Hi everybody, I am Philippe Faes, founder of Sigasi. Sigasi sells a design entry and code comprehension tool for VHDL. Many users of Altera Quartus have asked us if Sigasi plugs in to Quartus. We hav... Read more »


Job - Promotion - 2D/3D Bildverarbeitug - FPGA

Stellenausschreibung - Echtzeit-2D/3D Bildverarbeitung ------------------------------------------------------ Verg. Gr. 13 TV-L zu besetzen. Schwerpunkt der Forschungsarbeiten liegt auf dem folge... Read more »