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There are 82999 individual articles here that are part of 15165 discussions
Please see below the list of the most recent and the best rated articles in Field-Programmable Gate Arrays

The most recent discussions

FPGA sensitivities


September 25, 2020, 7:16 pm

I have a time-critical thing where the signal passes through an XC7A15 FPGA and does a fair lot of stuff inside. I measured delay vs some voltages: 1.8 aux no measurable DC effect 3.3 vccio ... Read more »

Active HDL Entity Retention


September 25, 2020, 5:31 pm

I have multiple entities in a file. I renamed one of them. The design bro wser now shows both the old entity and the new one. It won't allow me to d o anything with the old entity like delete it... Read more »

Multi-FPGA Interconnection: latest techniques


September 24, 2020, 10:52 am

Hi Experts, In FPGA Prototyping/Emulation flows, Multi-FPGA partitioning puts limitation on performance due to limited IO pins. What are the latest Multi-FPGA Interconnection techniques availabl... Read more »

Is there any way to get a different font for code sections?


September 22, 2020, 10:04 pm

When I make posts to this forum and have code to show, I do something like this: [code] module xyz (); // ... endmodule [/code] This has worked on other forums, creating a window with the tex... Read more »

How powerful is Verilog at using parameters to specify designs?

  [ 2 ]
September 21, 2020, 10:23 pm

I have a design in mind that would fit in this skeleton: [code] module xyz ( result, leftOp, rightOp); parameter integer nmBits = 1; localparam integer highBit = nmBits - 1; output ... Read more »

Exponential Regression by XSG


September 21, 2020, 11:05 am

I want to perform an exponential regression function by using the Xilinx system generator. To support fixed-point data, 12 bit, and 1 MSPS. That to estimate a logarithmic increase and decrease the ... Read more »

exponential regression in XSG


September 20, 2020, 4:01 pm

Hi Guys, I hope everybody is fine. I would like to perform an exponential regression function by using the Xilinx system generator. could you please make help me. thanks and regards M. I. Ibrahi... Read more »

Is it illegal to use an (enum) as a Verilog function input?


September 17, 2020, 1:24 am

I'm still very much interested in finding out whether or not it's possible for a Verilog function to have a boolean value as input, but while I was wa iting for input on that I decided to rewrite ... Read more »

Can anyone explain "cannot currently create a parameter of type" ...


September 17, 2020, 1:22 am

I've written a piece of code with inputs (left) and (right) and output (result), each of which operand is a single bit, which returns a logical one in (result) if (left) has the same value as (right)... Read more »

Can a Verilog function take a boolean argument?


September 17, 2020, 1:18 am

I've got a Verilog function that I'd like to behave slightly differently depending on the value of a boolean argument, an argument whose value can be either (true) or (false). I tried: [code] modul... Read more »

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The best rated discussions

rating
5

Microchip UNI/O controller core for FPGA


Hi, I needed to access the Microchip 11AA02E48 EEPROM located on a FPGA board. Unfortunately, I couldn't find any VHDL/Verilog sources of a UNI/O controll er. Therefore, I have decided to writ... Read more »

rating
5

Lowest Power Design in an FPGA


What is the lowest power design you have done in an FPGA or CPLD? There have been some very low power devices on the market for a number of years now. I assume there have been some designs that... Read more »

rating
5

VHDL BFMs and VVCs for AXI4-Lite, Avalon-MM, UART, I2C and SPI - for free ...


UVVM - the new VHDL verification methodology is a very good way to structur e your VHDL testbenches - and to make easily understandable, maintainable, extendible and reusable testbench architectur... Read more »

rating
5

Software for FPGA-based PC scope


Hello, Although I am a newbie in FPGA design and have experience only with some simple designs so far, I am thinking of some more ambitious project and want to design a FPGA-based PC scope working in... Read more »

rating
5

lowest-cost FPGA and CPLD


I heard that Lattice Semiconductor Corporation boasted they were providing the lowest-cost FPGA and CPLD solutions, not sure if the news was true. Could anybody confirm it? If so could anybody give m... Read more »

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5

ICTP Open Hardware Initiative – Invitation to part icipate in an open-surve...


Dear Colleagues / Friends We would like to invite you to participate in an important survey regarding an open FPGA Hardware initiative by the International Center for Theoretical Physics (ICTP - UN... Read more »

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5

Call for beta users for Sigasi integration with Altera Quartus


Hi everybody, I am Philippe Faes, founder of Sigasi. Sigasi sells a design entry and code comprehension tool for VHDL. Many users of Altera Quartus have asked us if Sigasi plugs in to Quartus. We hav... Read more »

rating
4

Job - Promotion - 2D/3D Bildverarbeitug - FPGA


Stellenausschreibung - Echtzeit-2D/3D Bildverarbeitung ------------------------------------------------------ Verg. Gr. 13 TV-L zu besetzen. Schwerpunkt der Forschungsarbeiten liegt auf dem folge... Read more »