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Please see below the list of the most recent and the best rated articles in Field-Programmable Gate Arrays

The most recent discussions

Is there any software I can use to transform state machines in VHDL into dr...


September 8, 2021, 8:24 pm

Hi, I have designed many state machines in VHDL, and I hope to use any software to transform the state machines in VHDL into drawings. Is there any software I can use to transform state machines in... Read more »

GDB from my university...


August 15, 2021, 7:17 pm

CS302 ? Digital Logic Design Graded Discussion Board You are required to program a PAL device to design a 64-bit counter. The st ated PAL can be programmed using ABEL (Advanced Boolean Expression ... Read more »

PLL dynamic phase shift


August 1, 2021, 5:02 pm

Why ck_dynamic is having period of 0.822ns when it is stated to be of 333MHz frequency? https://i.imgur.com/Rr1jS8Q.png https://i.imgur.com/jgfvxk6.png Read more »

A state machine design problem


July 8, 2021, 2:56 pm

Hi, I have the following VHDL code for a state machine: type Output_State_t is ( State_a, State_b, State_c); signal Output_State, Output_State_NS : Output_State_t ; At a clocked process, there... Read more »

Synthesis : Pan's Algorithm


July 8, 2021, 1:25 pm

Have anyone studied Pan's Algorithm previously ? http://people.eecs.berkeley.edu/~alanmi/publications/2005/iwls05_smr.pdf#page=3 https://i.imgur.com/GO8s4BU.png 1. How is Pan's algorithm being... Read more »

Why Xilinx Ten Gigabit Ethernet PCS/PMA IP Core 32-bit version use less res...


July 3, 2021, 4:43 am

The 32-bit version should have better latency performance but I think it's more complex, so it should use more resources. But as the link below https://www.xilinx.com/html_docs/ip_docs/pru_files/t... Read more »

Measuring ps of delays in FPGAs


June 21, 2021, 1:49 pm

Hi FPGA Experts, How can we measure ps of delays in FPGA with minimum area and good accuracy ? Today's TDC (Time to Digital Converter) architectures suffer lot of drawbacks like high gate utili... Read more »

How long does it take to fill up an array prior to sorting?


June 21, 2021, 2:42 am

Most sorting algorithms I've noticed seem to have an interface somewhat lik e this: void someAlgorithm ( elemType[] elements); So to implement this algorithm an application needs to fill the {elem... Read more »

A loop problem which does not do what is expected


June 18, 2021, 2:32 pm

Hi, I have a problem that does not do what is expected. I have several modules linked together from top to bottom. Each module has 3 error output signals: Error_O, Error_Level_O, and Error_Code_O. ... Read more »

Enterpoint dev board manuals


June 18, 2021, 8:01 am

Hi folks, It looks like Enterpoint (www.enterpoint.co.uk) has closed down. I've got one of their Drigmorn2 dev boards and some of the addon modules. Does anyone have a copy of these documents? - Et... Read more »

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The best rated discussions

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5

Microchip UNI/O controller core for FPGA


Hi, I needed to access the Microchip 11AA02E48 EEPROM located on a FPGA board. Unfortunately, I couldn't find any VHDL/Verilog sources of a UNI/O controll er. Therefore, I have decided to writ... Read more »

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5

Lowest Power Design in an FPGA


What is the lowest power design you have done in an FPGA or CPLD? There have been some very low power devices on the market for a number of years now. I assume there have been some designs that... Read more »

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5

VHDL BFMs and VVCs for AXI4-Lite, Avalon-MM, UART, I2C and SPI - for free ...


UVVM - the new VHDL verification methodology is a very good way to structur e your VHDL testbenches - and to make easily understandable, maintainable, extendible and reusable testbench architectur... Read more »

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5

Software for FPGA-based PC scope


Hello, Although I am a newbie in FPGA design and have experience only with some simple designs so far, I am thinking of some more ambitious project and want to design a FPGA-based PC scope working in... Read more »

rating
5

lowest-cost FPGA and CPLD


I heard that Lattice Semiconductor Corporation boasted they were providing the lowest-cost FPGA and CPLD solutions, not sure if the news was true. Could anybody confirm it? If so could anybody give m... Read more »

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5

ICTP Open Hardware Initiative – Invitation to part icipate in an open-surve...


Dear Colleagues / Friends We would like to invite you to participate in an important survey regarding an open FPGA Hardware initiative by the International Center for Theoretical Physics (ICTP - UN... Read more »

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5

Call for beta users for Sigasi integration with Altera Quartus


Hi everybody, I am Philippe Faes, founder of Sigasi. Sigasi sells a design entry and code comprehension tool for VHDL. Many users of Altera Quartus have asked us if Sigasi plugs in to Quartus. We hav... Read more »

rating
4

Job - Promotion - 2D/3D Bildverarbeitug - FPGA


Stellenausschreibung - Echtzeit-2D/3D Bildverarbeitung ------------------------------------------------------ Verg. Gr. 13 TV-L zu besetzen. Schwerpunkt der Forschungsarbeiten liegt auf dem folge... Read more »