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There are 82832 individual articles here that are part of 15139 discussions
Please see below the list of the most recent and the best rated articles in Field-Programmable Gate Arrays

The most recent discussions

Lattice new 28nm series - any clues about availability ?

June 29, 2020, 6:16 am

Just a few days ago, they presented Certus-NX series that is based on their new Nexus platform. Has anyone here been testing these and what else can we expect on 28nm ? Will there be ECP3 and XO3 s... Read more »

<whine mode on> Why is my source buried in the bowels of the project?...

June 20, 2020, 8:49 pm

I've always found it awkward that when I create a project the various tempo rary files the tool creates are at the top of the project tree and my files are down at the end of a branch of the subdi... Read more »

Driving crystal with cheap FPGA ( MAchXO2) directly ?

  [ 2 ]
June 16, 2020, 9:20 am

I tireid using ust a pin pair and inverting function. But with LVCMOS333 on Breakout Board ( 3,3V for I/O), MachXO implements hysteresis on input and this seems to hamper the oscillations. I can't ... Read more »

Lattice Diamond/LSE Synthesis - implementing ring oscilator in Verilog ?

June 14, 2020, 6:18 am

I can't do it. Every time I try, LSE reports combinatorial loop and optimizes whole thing away. I tried using attributes syn_preserve, syn_keep and syn_noprune, but the result is the same. LSE M... Read more »

enum and Vivado

June 5, 2020, 3:34 pm

I'm clearly failing to understand how enums are supposed to work in SystemVerilog. I've created a header file with the enum definition. I `include that header file in two files that want to use t... Read more »

Looking for MMI M2018 LCA data sheet

May 15, 2020, 4:50 pm

Hello, I'm a collector and tinkerer of old, archaic devices, and I recently came across a MMI M2018-20CP (date code 81xx) in a PGA package. I've found the M2064 data sheet, but I can't seem to tr... Read more »

fixed point modeling tools

May 6, 2020, 6:28 pm

Hello, For those of you who do DSP modeling in Python, I've recently released a pa ckage that supports fixed point arithmetic. The existing open source tools are lackluster and MATLAB doesn't ni... Read more »

Passing digitized data to design

May 6, 2020, 3:36 am

Hello, Is there a resource that can help me understand how to pass digitized data (from a waveform) to a design that I have for verification? I'm getting int o FPGA development and have created a... Read more »

CFP IEEE International Conference on Computer Design (ICCD) 2020

April 17, 2020, 2:53 pm

------------------------------------------------------------------ Call for Papers ------------------------------------------------------------------ 2020 IEEE Inte... Read more »

Custom CPU Designs

April 16, 2020, 3:51 am

In the Forth language group there are occasional discussions of custom proc essors. This is mostly because a simple stack processor can be designed to be implemented in an FPGA very easily, takin... Read more »

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The best rated discussions


Microchip UNI/O controller core for FPGA

Hi, I needed to access the Microchip 11AA02E48 EEPROM located on a FPGA board. Unfortunately, I couldn't find any VHDL/Verilog sources of a UNI/O controll er. Therefore, I have decided to writ... Read more »


Lowest Power Design in an FPGA

What is the lowest power design you have done in an FPGA or CPLD? There have been some very low power devices on the market for a number of years now. I assume there have been some designs that... Read more »


VHDL BFMs and VVCs for AXI4-Lite, Avalon-MM, UART, I2C and SPI - for free ...

UVVM - the new VHDL verification methodology is a very good way to structur e your VHDL testbenches - and to make easily understandable, maintainable, extendible and reusable testbench architectur... Read more »


Software for FPGA-based PC scope

Hello, Although I am a newbie in FPGA design and have experience only with some simple designs so far, I am thinking of some more ambitious project and want to design a FPGA-based PC scope working in... Read more »


lowest-cost FPGA and CPLD

I heard that Lattice Semiconductor Corporation boasted they were providing the lowest-cost FPGA and CPLD solutions, not sure if the news was true. Could anybody confirm it? If so could anybody give m... Read more »


ICTP Open Hardware Initiative – Invitation to part icipate in an open-surve...

Dear Colleagues / Friends We would like to invite you to participate in an important survey regarding an open FPGA Hardware initiative by the International Center for Theoretical Physics (ICTP - UN... Read more »


Call for beta users for Sigasi integration with Altera Quartus

Hi everybody, I am Philippe Faes, founder of Sigasi. Sigasi sells a design entry and code comprehension tool for VHDL. Many users of Altera Quartus have asked us if Sigasi plugs in to Quartus. We hav... Read more »


Job - Promotion - 2D/3D Bildverarbeitug - FPGA

Stellenausschreibung - Echtzeit-2D/3D Bildverarbeitung ------------------------------------------------------ Verg. Gr. 13 TV-L zu besetzen. Schwerpunkt der Forschungsarbeiten liegt auf dem folge... Read more »