Latest threads in Field-Programmable Gate Arraysshow only best voted threads

Subject Author Posted Replies
 
Wide frequency range, arbitrary waveform DDS
To generate frequencies from approximately 0.5 mHz to 12 MHz with a DDS a minimum clock of >24, say 25 MHz, is required. To be able to go down to 0.5 mHz, a phase accumulator of at least 36 bits is...
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Efinix FPGA
Anyone using Efinix parts? They look ok, even if they don't have a lot of package offerings. The smallest part has a 0.5A surge at power on. The list it as "minimum", I'm guessing they mean the...
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Getting Rank of Elements in an Array using VHDL
Dear VHDL Coders, I am trying to get the rank of elements from an array of data. For example, I have an array, Voltage = [20 40 10 30] ; The position of the elements in the voltage array is ranged...
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Development tools for Xilinx Spartan 3
For support of an old product, we may need to modify a Xilinx Spartan 3 FPGA. This was originally designed in VHDL with Modelsim Designer and ISE 9.2, both no longer available. New Vivado versions do...
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Calculation of throughput of sub-block in digital design (I)
I am trying to understand the correct way to calculate throughput of a digital hardware design block that forms part of a bigger system. Here are the few scenarios: 1. DUT takes 10 clock cycles to...
 
Old versions of quartus
Intel have discontinued old versions or Quartus II. For my project, I really really need Quartus II 12.0. Does anyone know of a mirror or a way to obtain old versions? You cannot download from the...
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VHDL project. Connecting components to one component
Hello guys, I am student at high school interested in VHDL programming and post quantum algorithms. I have a code where algorithm is divided to three parts. Each part is a component. I would like to...
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BeMicro Cyclone III 64-bit drivers
I found my old BeMicro Cyclone III board laying around the other day and ha ppen to have a use for it - if I can get it running again. I know it's an a ncient board, but this project doesn't need...
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Is it possible to amplify weak lows and weak highs?
I am in possession of a book that says if the gate of an N-channel MOSFET i s low (say 0 volts), then the output is high impedance; and that if that ga te is high (say 5 volts), then the voltage at...
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How to Implement a Random Access Memory at the Transistor Level
I don't know if this is the right forum to post this to. If there's a forum that would be more appropriate for a question like this, please let me kno w. Let's say for a moment that I need to build a...
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Verilog HDL Finite State Machine - detecting a decimal number
Hi all, I am trying to build a sequence detector to detect a decimal number like 10 92 when a stream of numbers from 0-9 is given as input. Do you think just c hanging the width of input i.e parallel...
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Quartus II Synthesis - System Memory Issues for Large Stratix 10 Design
Hello, I have a Stratix 10 design that is based around an ip core generated using Intel's HLS. The core does some simple floating point operations and by its elf uses very few resources (1 DSP, a few...
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UDP -FPGA point to point
Hello everyone, I have recently started working on a project using Ethernet in an FPGA and I am using the UDP protocol for communication between the PC and the FPGA. The communication is happening...
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Xilinx forums have disappeared?
Today I tried to find certain old post on the Xilinx forum. Goggle has found it in their database, but the link leads to nowhere and is finally redirected to . There is no forum available any more....
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Is there any software I can use to transform state machines in VHDL into drawings?
Hi, I have designed many state machines in VHDL, and I hope to use any software to transform the state machines in VHDL into drawings. Is there any software I can use to transform state machines in...
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