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There are 83442 individual articles here that are part of 15240 discussions
Please see below the list of the most recent and the best rated articles in Field-Programmable Gate Arrays

The most recent discussions

Magellan VHDL monitor for Basys 3 board


September 24, 2022, 8:36 am

Magellan HW monitor for Basys 3 board - Access register banks for reading/writing via JTAG to AXI adapter. Can also monitor register values via the board seven-segment display (register address is se... Read more »

Hardware based IP protection of FPGA designs


September 24, 2022, 7:41 am

My customer is asking for a redesign of a very profitable board to deal wit h components that are EOL. Because of delivery issues from the EOL compon ents, they are asking for the IP and manufact... Read more »

Last CFP: 22nd International Conference on Hybrid Intelligent Systems (HIS'...


September 9, 2022, 4:36 am

* Final Call for Papers - please circulate this CFP to your colleagues and networks ** We are sending you an invitation for the 22nd International Conference on H ybrid Intelligent Systems (HIS'2... Read more »

Wide frequency range, arbitrary waveform DDS

  [ 2 ]
August 16, 2022, 3:37 pm

To generate frequencies from approximately 0.5 mHz to 12 MHz with a DDS a minimum clock of >24, say 25 MHz, is required. To be able to go down to 0.5 mHz, a phase accumulator of at least 36 bits is... Read more »

2nd CFP: 18th International Conference on Information Assurance and Securit...


August 7, 2022, 8:31 am

** Second Call for Papers - please circulate this CFP to your colleagues an d networks ** -- 18th International Conference on Information Assurance and Security (IAS 2022) -- http://www.mirlabs.... Read more »

Efinix FPGA


July 12, 2022, 12:25 am

Anyone using Efinix parts? They look ok, even if they don't have a lot of package offerings. The smallest part has a 0.5A surge at power on. The list it as minimum, I'm guessing they mean the min... Read more »

Getting Rank of Elements in an Array using VHDL


June 21, 2022, 2:51 pm

Dear VHDL Coders, I am trying to get the rank of elements from an array of data. For example, I have an array, Voltage = [20 40 10 30] ; The position of the elements in the voltage array is ranged ... Read more »

First CFP: The 12th World Congress on Information and Communication Technol...


May 20, 2022, 5:29 pm

** First Call for Papers - please circulate this CFP to your colleagues and networks ** -- The 12th World Congress on Information and Communication Technologies (W ICT'22) -- http://www.mirlabs.... Read more »

First CFP: 13th International Conference on Innovations in Bio-Inspired Com...


May 16, 2022, 10:13 am

** First Call for Papers - please circulate this CFP to your colleagues and networks ** -- The 13th International Conference on Innovations in Bio-Inspired Computing and Applications (IBICA'22) --... Read more »

First CFP: 14th World Congress on Nature and Biologically Inspired Computin...


April 27, 2022, 8:27 am

** First Call for Papers - please circulate this CFP to your colleagues and networks ** -- 14th World Congress on Nature and Biologically Inspired Computing (NaBIC 2022) -- http://www.mirlabs.n... Read more »

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The best rated discussions

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5

Microchip UNI/O controller core for FPGA


Hi, I needed to access the Microchip 11AA02E48 EEPROM located on a FPGA board. Unfortunately, I couldn't find any VHDL/Verilog sources of a UNI/O controll er. Therefore, I have decided to writ... Read more »

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5

Lowest Power Design in an FPGA


What is the lowest power design you have done in an FPGA or CPLD? There have been some very low power devices on the market for a number of years now. I assume there have been some designs that... Read more »

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5

VHDL BFMs and VVCs for AXI4-Lite, Avalon-MM, UART, I2C and SPI - for free ...


UVVM - the new VHDL verification methodology is a very good way to structur e your VHDL testbenches - and to make easily understandable, maintainable, extendible and reusable testbench architectur... Read more »

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5

Software for FPGA-based PC scope


Hello, Although I am a newbie in FPGA design and have experience only with some simple designs so far, I am thinking of some more ambitious project and want to design a FPGA-based PC scope working in... Read more »

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5

lowest-cost FPGA and CPLD


I heard that Lattice Semiconductor Corporation boasted they were providing the lowest-cost FPGA and CPLD solutions, not sure if the news was true. Could anybody confirm it? If so could anybody give m... Read more »

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5

ICTP Open Hardware Initiative – Invitation to part icipate in an open-surve...


Dear Colleagues / Friends We would like to invite you to participate in an important survey regarding an open FPGA Hardware initiative by the International Center for Theoretical Physics (ICTP - UN... Read more »

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5

Call for beta users for Sigasi integration with Altera Quartus


Hi everybody, I am Philippe Faes, founder of Sigasi. Sigasi sells a design entry and code comprehension tool for VHDL. Many users of Altera Quartus have asked us if Sigasi plugs in to Quartus. We hav... Read more »

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4

Job - Promotion - 2D/3D Bildverarbeitug - FPGA


Stellenausschreibung - Echtzeit-2D/3D Bildverarbeitung ------------------------------------------------------ Verg. Gr. 13 TV-L zu besetzen. Schwerpunkt der Forschungsarbeiten liegt auf dem folge... Read more »