Zilog's new ZNEO info appearing

This seems very interesting! Zilog typically charges a bit too much for their MCUs (their Acclaim costs more than many Arms that outperform it by a wide margin), but the ZNEO prices posted at Mouser seem to be very competitive. This will be something to watch.

Eric

Non-stock, every one. Perhaps prices may change when they actually get some parts to ship?

Jon

Of course - that's because this is 'pre launch web leakage'.

The $99 eval kit shows delivery due late this month, and the devices show a few more weeks out. (fairly typical new product roll-out)

There is not much point in Mouser playing loose on prices: The buy button seems to be alive, and stock is shown as on order.

Looks like ZiLOG will be in a position quite similar to Freescale, who also pitch a "common tool chain", and have a new Coldfire V1 core 'comming', but further out than ZENO.

-jg

My concern is that this device will become another eZ80 (Acclaim and a few other parts), which is to say orphaned. Zilog has put all of there efforts into the Encore and is not developing the ez80 hardware. They are doing software for the ez80, but they would be better off sub-contracting that because it is not a core business.

Dave,

Hehe. Okay. I do wonder, sometimes.

I'll be looking at the parts, at least. No specific application in mind, just to be aware for now.

Thanks, Jon

This is a most unusual rollout.

Now, Digikey show stock, so seems you can BUY the devices, and program them, but Zilog have not yet posted data sheets ?!

Normally, the press releases and prelim data, are months ahead (sometimes years ahead! :) of the usable silicon.

-jg

I suppose they don't really care if you use them for pet rocks, jewelry, or whatnot; just so long as you buy them. ;)

Jon

More data is now up at

Looks like quite a significant device:

Speed is not stellar, but is adequate for Energy/Motor usage, and general uC usage, especially given the wide data types.

Zilog call this 16 bit?, (Z16F) but it DOES have 16 x 32 bit registers, and MUL and DIV of 32x32 to 64 bit result, and 64/32 divide ! Probably that tag is to give them some 'marketing space'

Register MAP is very similar to ARM, but ARM7s lack the Divide opcode. ZNEO has many efficent opcodes, like DJNZ and short jumps, and supports direct memory opcodes! (unlike many RISC cpu's, that use a lot of code doing load/store) It does support 8, 16, and 32 bit types, and has variable length opcodes. Includes an ATOMIC opcode for flag integrity.

When more info comes from Feescale on the V1 coldfire ( 8 bit peripherals, and common tools), they may be very similar in coverage: Zilog's Z8F to ZNEO, and Freescale's RS08 to V1 Coldfire.

• Available also in PLCC68 - So makes this a _socketable_ 32 bit register microcontroller (a rare thing). That will be student friendly.

• Models in 80/100p include external bus ( ISA mode )

• Models in 105'C and 125'C - others thin out there, or get expensive.

• On Chip debug, USB debugger and C compiler (limits?) seem to all be included in the eval system. That's a price/tool point others struggle to meet.

• Eval PCB has the Flash uC, with also 1MByte FLASH and 256KByte SRAM, so that's rather Rabbit like. [but just 2 UARTS, and no Ethernet]

• Good peripherals, SPI / UART / IrDA / 6 Ph PWM / Comp / OpAmp etc ( as one would expect from Zilog, they've been doing UARTs since adam was a boy.. )

• ALL from one supplier: CPU docs, Peripheral Docs, Debugger, Compiler, Assembler.

Missing: No Up/Dn counters, and no register frame pointer, or register bank switching. Given their Z8 core, that could have been expected ? No boolean opcodes.

Who should be worried ? ZNEO fits above AVR8 (8 bit, no external bus), and under AVR32 (32 bit, no on chip flash). PIC18 / dsPIC would be interesting comparison. ST10/XC166 - mainly 16 bit registers, ARM7: Quite similar, so at the HLL level, probably little culture shock expected. Freescale : depends on new V1 coldfire. Zilog may have got there first ?

-jg

It's memory buses are 16-bit and it can't compete with existing 32-bits chips (multiplies taking up to 18 cycles, shifts taking up to 32 cycles?!?), so they chose to call it 16-bit instead.

Cortex-M3 has divide of course. Div64 is a nice detail though.

It's clear ZNEO is a 68000 clone, it's very CISCy. Call12 is good for codedensity, but the 48-bit direct memory addresses are overkill, people will avoid these because they are slow and bad for codesize. The same is true of the memory-op-memory operations, they seem nice at first until you experience the slowdown they give. There are good reasons RISC is more widely used nowadays...

Coldfire and ZNEO are very similar indeed, almost identical instruction set. The ZNEO is much slower but at least got rid of the worst mistakes of the 68K: the 8/8 register split and the 2-memory address instructions.

Wilco

cycles?!?),

Multiples have early-out, but its still 10 cycles. So, yep, pretty poor by

32-bitter standards. The shifts that take 32 cycles are the 2 register (64-bit ones). The normal shifts max at 10 cycles as far as I can see (3+7).

PC is *not* part of the general register set.

Indeed.

opcodes.

They still seem muddled as to what is architecture and what microarchitechture though. Instruction cycle times are in the doc section as part of arch, which means to me that a new conforming implementation must keep the same cycle counts. I'm fairly sure thats not what they mean though.

Peter

You can say that again. And they do include the block for "instruction state machine" in their block diagram of the CPU, so luckily I don't think they aren't going to try and argue this is RISC.

Jon

Thanks for the update. I took a look and it's probably not a good fit for most things I care about.

By the way, in my 5-minute skim of the CPU description I noticed that they mentioned that the non-volatile memory map appears limited to the low 64k region (perhaps even 32k, if I read their dashed rectangle right) but the first parts that Mouser says they have include 128k of flash, I think. Looks like at least some, if not all of it, must be connected internally to the external memory bus interface. But I'm not sure about that. Anyone know what the score is, here?

(The two parts that Mouser says they have in stock are the QFP-80 and the LQFP-100 packages of the Z16F2811. I note that the 100 pin variety is listed as cheaper than the 80 pin _and_ that Mouser's search engine considers "on order" as "stocked," when asking only for stocked items.)

Jon

I did not see any 48 bit memory loads, ( Addr16 & addr32 tho ?) If you look at the % of code RISC wastes doing IndexLoad/varload/Varstore then direct memory opcodes can help a lot, plus they are more naturally atomic. Few CPU architects seem to grasp the big picture, and couple the on chip memory to the CPU well - they design microprocessors, not microcontrollers. The XC166 is one of the few that does this well.

-jg

I meant the 32-bit absolute address which means 48-bit instructions. These are a bad idea for codesize as you repeat the same 32-bit immediates again and again. And with 16-bit fetch they add 2 cycles whenever used... Removing them would simplify the instruction set to a mix of 16 and 32-bit instructions and leaves more space for extensions. So why add them? To be more like 68000/Coldfire?

Memory-operate-memory instructions are a microarchitectural nightmare, it is very difficult to get higher clockspeeds without doing what x86 does (splitting into RISC instructions and execute them out of order). The benefits are overrated, remember we did a comparison a while ago where it turned out the difference is small.

The big picture is that you want an architecture that allows all sorts of memory systems, from tiny MCUs too big cached systems. That means keeping the architecture are generic as possible and only optimise the micro architecture for special memories.

Wilco

It's 10 cycles for 16-bit multiplies indeed. Various CPUs can do

32-bit multiplies in 1 cycle, so it's clearly not meant for DSP...

You're right. That reminds me of the tricks I used to play some 20 years ago: do a right shift by 8 and then add with carry rather than shifting by 7. The 2-instruction version takes 2 cycles, the obvious shift by 7 takes 7... It's insane to do something this CISCy in 2006. Barrel shifters and multipliers are not very large.

Yes, what they call "architecture" is what we call "micro architecture". Just about everything else in the document appears to be architecture. There is also confusion about load and store, both of which are called "LD". I guess this is Z-80 history showing through.

Wilco

In a microcontroller the 32 bitloads would be rarely used.

I see they have smaller signed offset opcodes : soff14 to reg and PC (2 words), and soff6 to FP (one word) They also have a single word conditional jump, rel8.

I'd probably agree in a microprocessor, with a lot of memory elasticity.

- but that is not a microcontroller.

To me, that sounds like "jack of all trades, master of none" thinking, skewed to the microprocessor end, which was exactly my point.

-jg

Exactly my point, the way they ignore the most significant 8-bits of the address (a well known mistake in 68K) means you can access 32KB of flash and 32KB of RAM/IO with an 16-bit absolute address.

Yes, like 68K, offsets cost you an extra word - bad for codesize as loads with offsets are very common.

I'm surprised by soff6 to FP - with 14 registers available few things go on the stack, so FP based loads should be very rare. I'm sure they mandate frame pointers, LINK instructions and force all arguments to be passed on the stack. Oh yes, back to 70's CISC style...

The boundary between microprocessors and microcontrollers is very small. The same cores are often used in both variants - the main difference is on-chip memory.

General purpose is the word. The basic idea is to streamline the architecture as a whole so that it can do everything well. Even if some things take a few more instructions, RISCs like ARM produce smaller and faster code overall. It's not a coincidence that almost all 32-bit chips are RISC.

Wilco

... and finally Zilog make a press release about this device ! (that's a strange roll-out, but interesting device ) mentions "from $6.00 to $8.00 at 500-unit quantities".

they also have a contest running, for those with free time ...

looks quite cheap (subsidised) : $49.95 for USB Debug/Large PCB/C Compiler/Debug.

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-jg