PIC/AVR serial modes

You can do whatever you like if you implement it yourself in software.

Leon

Sure, but the idea was to use a builtin hardware USART to reduce the cpu load.

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If you use a part that has an SPI interface with DMA, that will (kinda) give you what you want.

Some of the newer AVRs has a synchronous serial mode for the UART. One can program 5 bits per character mode, and send 2 in synchronous mode. Regards Anton Erasmus

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You can send any string of bits using the SPI interface.

Meindert

That work for open collector or RS485 bus too..?

..?

Of course. The SPI output is just a serial output, just like the UART TX output. You can add anything to that port, an open collector stage, a MAX485, anything.

Meindert

SPI has three signal lines. My bus is only 1-bit "wide" (open collector). So somehow clock + data must be joined.

If you want to encode clock information in your data stream you have to do it before writing it to the SPI register. SPI is basically a parallel in serial out register on the transmit side, and a serial in parallel out register on the receive side. If you keep loading 0x55 into the SPI DATA register you will get a clock signal of 1/2 the SPI clock on the MOSI pin. Keep loading 0x0F, and you will get a clock at 1/8 of the SPI clock on the MOSI pin.

Regards Anton Erasmus

IIRC you wanted to create a serial signal without the boundaries of start and stopbits or a predefined word length. For that, you only need the SPI output (MOSI). You don't need to join clock and data. Or it must be that you want to do something more than you asked us...

Meindert

Now that's an idea. However there will be a problem to recover the clock on the receiving side.

If you use something like manchester encoding on your trasnmit side, you are guaranteed an edge at least every second bit. On your Rx side you can use a Phased Locked Loop to align a local clock with your data stream clock.

Regards Anton Erasmus

Can this PLL be accomplished without external components ..?

Depends on your data rate. In principle it is possible. You may also be able to decode using an edge triggerred interrupt on a GPIO pin. A negative edge is a 0 and a positive edge is a 1.

Regards Anton Erasmus

What? By definition, Manchester encoding has an edge *every* bit at the centerpoint, where the direction of the edge indicates the data bit being encoded.

I prefer the variant where there is a transition at the start of every bit and another transition in the center if the bit is a 1. I think it is called 'Biphase-S' (of FM). It has the benefit that it is insensitive to the polarity of the signal and very easy to sync to the start of a bit.

What Anton may have been referring to is MFM as used on disk controllers.

You are correct. I meant compared to the original clock, the manchester data stream has an positive edge at least every second clock period.

Regards Anton Erasmus