PSRAM needs a 17th bit in the data path .
It SBZ , but when the end of the low
level code comes along , the clk
to the PSRAM unknowningly clocks
a different address !
The CPU need not waste time "RETURNING" subroutine ! Its transparent RETURN .
I program low level primatives ,
ussually 16 ,
then higher level "midlevels" ussually 16K .
My 16 , low level "primatives" dont RETURN
subroutine , they use a JUMP table to
go directly to the next Primative , using
an indirect JUMP thru the jump table .
Its very clever and much faster than
anything you get with C++ !
Have you noticed , they will not make
this , even in the mature IBM PC !
all the memory pays a big $$ .
There is a burst mode , but no way
to nix the delay of re-addressing !
and it only takes 1 extra bit !
I could emulate it using parity RAM ,
but it would still waste a ram location ,
cause id have to read that DATA location .
They wont make it !!
At very low speeds , i'd use a EEPROM , serial , id only clock it at "cell" edges . I.E. , i would clock EEPROM at 1/16 the rate , and EEPROM is flashed to all "highs" . If my Primative needed more than 16 bytes , the EEPROM would be missing that High . This allows a tiny 2KB EEPROM to do much larger SRAM banks , since its only clocking 1/16 th .
Ultimately , buying the SRAM is the hassle , i need 1000 1MB SRAMs ...
Im doin ARM 144 pin CPU's ...