comp.arch.embedded counter 0 of atmega48
How is tcnt0 on the atmega48 started...??? The code below doesn't seem to have any effect. in areg, TCNT0 provides only a zero. The intent is a free running counter, up to 0xff and then to zero and up again. The PRR section section says "when tim/cnt0 is enabled, it works...". The tcnt0 section says roughly "...tim/cnt0 bit in PRR must be written to zero to enable tcnt0." Wogdog, below, shows just a continuous line at 0 volts on a scope. The definitions for the various symbols are at the bottom. And, I owe thanks to LAIRD for a suggestion to check those. All the definitions on that occasion were correct but some comments were not "commented out" resulting in, you guessed it, altered definitions. Back to this counter... it's the simplest configuration available - what's missing?
; timer0 power politics?? lds areg, PRR andi areg, 0xdf sts PRR, areg ; timer0 cntl A: ldi areg, 0 ; no output compare or pwm sts TCCR0A, areg ; timer0 cntl B: ldi areg, 5 ; sets clk/1024 sts TCCR0B, areg
wogdog: in areg, TCNT0 sbrs areg, 7 cbi TPOUT, TPHNUM sbrc areg, 7 sbi TPOUT, TPHNUM rjmp wogdog
PRR $64 TCCR0A $24 TCCR0B $25 TCNT0 $26 areg r16