VCC voltage pin: whats an acceptable range

LOL

It was so sad when she backed into the corn chopper - disaster.

Bob

A 6264 only draws 30mA or so, and that's when active. It should not cause a 0.2V drop in Vcc just by being there.

OTOH, if your address decoder/read/write decoder is enabling more than one device to write to the data bus at any point in time, you will have one device trying to pull high, another trying to pull low, start sucking a lot of power, AND nothing will work right.

Just my 2 cents: not tri-stating your drivers at the right time is the cause of 95% of the woe in a beginner's circuit like this. Look closely at OE/CS of not only the SRAM, but also of your ROM and anything else (I/O?) you have there.

Poor bypassing could contribute to this, lord knows lots of things can go wrong on a protoboard without a ground plane, but you're only running at a MHz or so, right? That masks a lot of grounding/bypassing sins. Turning CS on and off to the RAM might cause enough of a change in current draw to make better bypassing necessary, though.

Tim.

newbie: I know VCC on TTL chips should be tied to the 5v line. I am curious whats an acceptable range ... meaning how low or how high can this value be

would 4.5v be acceptable? 5.5v ?

I am going to have to dig into old text books on this. some background: I am a software engineer who is designing an sbc (based around the 6502) as a hobby. recently I have been trying to track down the cause of a weird problem i am seeing.

with the 6502+rom+i/o register (implemented with 74245+74573) in the circuit ... it operates as expected and Vcc NEVER dips below 4.92v ... once I connect a 6264 sram (chip enable decoder lines are handled by a PAL, data and bus lines are connected appropriately), Vcc drops to 4.7v ... and my circuit isnt operating as expected.

I remove the SRAM ... its fine. I tested the SRAM in my universal device programmer ... its ok

I'll need to dig into this further but I have been trying to debug it by single cycling (cmos version of 6502 use static registers so I can toggle its clk in lines) through the circuit after reset and using the DMM to verify the data read out of the ROM at each clock tick.

with the SRAM attached ... the output from the rom doesnt match what I expect.

ANyway I have the whole weekend to figure this out ... and already I am off on a tangent.

Whats acceptable values for VCC? thanks

Jim, good point thanks. I actually thought about that. I breadboarded this on one of those digital trainer boards with toggle switchs and led for testing your circuits. that trainer board provides 12v,-12v and 5v along with 100k clock and sine source

I wanted to see that my design on paper matched what I expected before I start making a PCB.

Guess Ill have to break out the old and RELIABLE Elenco PowerSupply. Its been years since I touched that box. Thanks

OE\\ should only be LOW (grounded) when READING from the chip. OE\\ should be HI all other times.

-Dave Pollum

Ouch. good point here. I have about 3 or 4 .01uf caps ... but since its on breadboard the leads are long.

Maybe I should just layout the board and make a PCB ... with bypass caps where they should be .. after all I am certain of its operation WITHOUT the SRAM ... (I have yet to add the UART and rs232 level converter ... thats all that will be in THIS version of the SBC).

That way I can test it in a compact manner. All the jumper wires and long leaded bypass caps maybe contributing to the problem I am seeing. A problem that didnt exist until I began to add more "load" to the circuit.

Thanks

Hilarious point taken!

It could be plain old power supply sag. I have built some pretty ambitious circuits on breadboard (10-12 TTL IC's with a microprocessor) that worked without a hitch (at least at room temperature). Each chip had one cap per VCC pin, with the shortest run I could manage between the ground bus and the power bus. Even on solderless protoboard you can do pretty well with a cap at the head of each IC and the shortest jumpers you can manage to the power pins.

If you have a scope look at your power supply -- if it's just sagging then you need something more stout. If it's got ripple then you need capacitors with values inversely proportional to the frequency of the ripple.

--

Tim Wescott
Wescott Design Services
http://www.wescottdesign.com

Well I did a quick review: the 6264 has two chip enable lines, and OE\\ and WE\\

I have OE\\ and CE1\\ grounded WE\\ is tied to the R output of my address decoder CE1 is tied to the RAM_CS output of my address decoder

From the tests done in the past the address decoder logic drives the pins as expected: heres a small sample:

/**********************/ ROM_CS=A15&RW_6502&O2_6502; RAM_CE0=!A15&!A14&!A13&O2_6502; UART_CS=!A15&A14&!A13&O2_6502;

IO_CS=(!A15&A14&A13&O2_6502&!RW_6502) # (A15&O2_6502&!RW_6502); NIO_CS=!IO_CS; /***************************/

I am going to be tearing through this system THIS weekend. I am positive there is no bad connections ... but Ill double triple check.

And of course the system is operational UNTIL I add the 6264 SRAM.

Ok Tim, Ill look into this .. thanks for the advice. Looks like its time to layout the PCB and build it ... and let this version serve as a "prototype"

I get a little chuckle when I get a customer support call that starts out with something along the lines of "What should my 5 volts be set at?" Well, how about, wait for it..... 5 volts. But seriously, the only way to answer that is to look at the datasheet of the part you are wondering about. TTL had a range of 4.75 to 5.25 as a min to max operating range, but on complex boards the odds of everything getting along together near one of the extremes is pretty slim. Some IC's are pretty picky on nice stable and clean power. If your power is dipping just by putting in another part (and the part is known good) I would suspect a bad power supply. Keeping +5 +/- .05V shouldn't be a big problem with any decent regulator.

Jim

From what I gathered he is pretty much single stepping the CPU and operating in the sub-1hz range. Now his edges are going to still be edges and decoupling caps should still be used. I didn't think about bus contention causing the power dip, but that could be a real issue.

Jim

Dave you are ABSOLUTELY RIGHT. I wish I read this post before I wasted a few hours on this:

Heres how I arrived at the same result: /*************? I ran a few experiments to try and further isolate the problem: the reset line (6502) is held down when I power up ... i toggle through 3 counts before I raise the reset line ... then I toggle for 6 counts which should place the processor in its reset vector at 0xfffc

1) verified that ADO - AD15 held the value 0xfffc using DMM 2) however DO-D7 registered 0xff instead of 0x0 (see devtest.lst) this is incorrect because on reset it should read 0x8000 from 0xfffc in ro the voltage level on D0-D7 was 2.45v 3) disconnected D0 jumper on ROM chip ... tested the voltage level on the pin it registered logic 0 and 0.82v 4) disconnected D0 jumper on SRAM chip ... tested the voltage level on the pin a it registered logic 1 4.25v

****interesting****

I double and triple checked the connections ... then thought that the only pin that could possibly be giving me trouble must be OE\\. this was based on the process of elimination.

addition of SRAM caused voltage fluctation on VCC and incorrect data values from ROM CE1\\ and CE2 are correctly connected/driven WE\\ is correctly driven ... OE\\ must be at fault, as its the only signal whose value does not matter when a write is in progress ... but must be held low during a read

AS A TEST I disconnected OE\\ (was tied to ground). with the pin floating its a logic

1. I ran a test and my circuit worked ... up until the point where I read from SRAM.

the manual is incorrect ... the 6264' OE\\ must be high at all times and low during the read cycle. In short I needed to drive it low under the following conditions:

1) SRAM is enabled (RAM_CS) 2) Read is in progress (RW_6502)

Don't do this. Drive OE\\ from the processor's "memory read" signal. Leaving the output enable permanently enabled will give you bus contention.

Good Luck! Rich

On "Proto-Board", (the kind with the little arrays of sockets), I've been known to use 2X 0.1 uF (100 nF) monolythic caps per chip. You _can't_ overcapacitate. :-)

Good Luck! Rich