I just came across an interesting chapter about temperature control in one of my books about transient thermal impedance (power electronics - converters, applications and design). A device is not only assigned a thermal resistance but furthermore also a thermal capacity. I wanted to use this for calculating the maximum time I can temporarily overload a semiconductor without any cooling. Sadly the manufactures do not supply these values.
Therefore I wanted to ask if somebody has such values for common semiconductor packages (e.g. sot-223) and certain device families. Of course for some semiconductors typically used for switching the manufacture provides such values or you can use the average power. But this does not apply for peak pules with a long delay between them.
Win Hill has certainly talked about this here, and may be able to come up with some ball-park figures.
Some semiconductor data sheets do give thermal derating curves as a function of the duration of the overload, and these can be translated into heat capacity figures. The heat capacity does change with the duration of the thermal pulse - for infinitesimal impulses the heat capacity is just that of the conducting channel itself, but over microseconds the channel substrate comes into the picture, and over longer periods the whole package has a chance to warm up.
Most power semiconductors have safe operating area (SOAR) curves on their datasheets. Some fets are specified to dissipate multiple kilowatts for short pulses.
Some of my higher-powered amplifiers have shutdowns based on computed/simulated junction temperature. An ADC measures everything (supply rails, output voltage, currents, heatsink temperature) and a processor runs a realtime simulation of junction temperature. The thermal mass of the fet chip and package is approximated as a single
1st order time constant. For TO-247's, based on experiments, we usually use 50 to 100 milliseconds.
Actually that used to be encoded in the safe operating area (SOA) curves. Specific data never was provided. If you are good enough, i suppose you could approximate it from device dimensions and thermodynamics.
Not even close, pretentious idiot. Bipolar SOA encompasses both thermal and avalanche effects , hence the I-V curves, and "specific" enough data was always provided. You're confusing SOA with the transient thermal impedance curves, again always provided for the power bipolar. You're not even qualified to answer questions in the basics ng, but isn't it typical that ignorant swine like you pretend to be in a position to publicize a rating of others. Too bad stupidity isn't immediately fatal...
Wish it were... Bloggs would be a victim, much to our delight ;-)
What don't you stop the name-calling and (at least) act like you're an intelligent contributor to this news group?
...Jim Thompson
-- | James E.Thompson, P.E. | mens | | Analog Innovations, Inc. | et | | Analog/Mixed-Signal ASIC's and Discrete Systems | manus | | Phoenix, Arizona Voice:(480)460-2350 | | | E-mail Address at Website Fax:(480)460-2142 | Brass Rat | |
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| 1962 | America: Land of the Free, Because of the Brave
You need to take a look at your fan club- the whizbang techies and hobby boys with the high school diplomas on the wall, big know-it-alls, and get a clue...
I paste a typical sample of Winfield Hill thermal analysis hereunder, from a Jan 2005 post. You can find the whole thread using Google Groups' advanced search function.
A logic-level FET is a good choice if one wants to use the FET's transconductance to establish a constant current electronic load. An IRL3716 would be a good choice for a 100A load, because 100A is close to the current at which it has zero transconductance tempco, with about a 2.9V gate voltage for Vds =3D 15V, see fig 3. I'd add a source degeneration resistor to better establish the current at different drain voltages. For example, a 0.02-ohm low-inductance resistor would drop 2V at 100A, and a 5.0V gate drive would bias the IRL3716 to sink about 90A for 8V to 100A for 15V on the drain. One can adjust the gate pulse voltage to trim the 100A current.
These FETs may be hard to get in the TO-220 version (the surface- mount versions, which have less thermal capability, are in stock), so an IRF IRL1404 or IRL2505 (Vgs =3D 3.8V), or a Fairchild FDP7045L (Vgs =3D 3.3V) can be considered instead.
Done this way, with the battery current dissipated mostly in the FET, each battery-test pulse has to be short, limited by the thermal mass of the MOSFET. The thermal mass parameter isn't given directly on the datasheet, but for a quick part search one can eyeball the FET's maximum Pd spec, which is usually on the front page. A low thermal resistance is required for a high Pd, and this usually implies a high thermal mass. To complete the calculation for the selected FET, one refers to the Maximum Effective Transient Thermal Impedance curves, e.g., fig 11 for the IRL3716. For example, let's assume our FET has about 10V across its D-S terminals during our 100A pulse, which would be 1kW dissipation. Assuming a 150C junction temp rise, we calculate a maximum allowed Thermal Response ZthJC =3D dT/P =3D 150C/1kW =3D 0.15C/ W, and examining the single pulse curve, we see that this corresponds to a maximum pulse duration of about 500us. This is consistent with the figure 8 Maximum Safe Operating Area plots.
Right, we're talking Ciss into the 5nF territory, which requires a 0.25A gate current for a 0.1us switching time (for a 5V pulse). A wimpy 10mA gate-drive capability, as from a CMOS 555 timer, could result in a rather slow 2.5us to 5us switching time. That's 1 to 2% of a say 250us test pulse.
Jim Thompson is reliably out of touch with reality, but this unusually unrealistic, even for him. Just for the record, Fred Bloggs may have his problems, but stupidity isn't any of them.
A question one might also direct at Jim, if one didn't know what the answer was going to be.
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