The Xilinx CoolRunner CPLDs are low power (like 10 or 20uA Iq), and pretty reasonably priced.
Best regards, Spehro Pefhany
The Xilinx CoolRunner CPLDs are low power (like 10 or 20uA Iq), and pretty reasonably priced.
Best regards, Spehro Pefhany
Define "low power" and "low cost".
I've found that the real cost of FPGAs was directly proportional to how tied you are to their architecture, and inversely proportional to how badly the manufacturer wanted to do business with you. The book prices mean absolutely nothing and quantities are only a secondary consideration. It really is an odd business.
We've recently got distributor pricing on one Altera part at $800, and another quote at $140.
I'm still impressed by the truncated triangle wave. Harmonics are surprisingly low, it only takes one op-amp, eliminates a lot of discretes, and has no difficulties with tolerance, stability, etc.
.-----[3k]----. | | | |\ +5 |
2.5Vpp | | \| | /\/\/ >--[1k]--+--|- \ | __ | >------+----> / \ / .--|+ / LTC6255 _/ \__/ | | /| === |/-5v 2nd: -39dB 3rd: -37dB 4th: -30dB 5th: -38dB
OK, but make sure that the opamp actually rails clean and recovers fast enough.
I still want a sine wave!
No magic involved. Just run the Fourier (by hand :-) of that truncated triangle and you'll see why it works. ...Jim Thompson
At what phase angle does the triangle wave clip? Maybe I'm missing something, but with a gain of 3 should a 2.5Vpp triangle wave clip a rail to rail op amp on +/-5?
It shouldn't and in my simulator, it doesn't.
Ye, I think a little mis-annotation there ;-) ...Jim Thompson
So, assuming for argument's sake that if the triangle wave coming out of the op amp would be 1 volt, at what voltage level do you clip it? To do the Fourier analysis you have to break the integral into 3 parts, and I'm betting not all clipping amplitudes are created equal. Is it right at the midpoint, like so:
Or are we to determine that as well?
1V Peak, 2V P-P Triangle. Clipped at +0.667V and -0.667V
I used to know a method, I think attributed to Heaviside, that gave a really easy way to Fourier waveforms made up of line segments. I remember some of it, but not all. I'm searching my notes ;-) ...Jim Thompson
I think "low power" is self evident. The iCE40 line has no comparison in the power arena. The only other remotely similar device I know of is a part from Actel that has a very low "sleep" power level. They don't talk about its active power level. The iCE40 devices have specs on power and you can get a power estimate from the design software once you have a design to estimate.
I won't comment on "low cost". I know the prices are variable to win sockets; that is true for all FPGAs including the iCE40 parts. But there is always some relationship to the book price since they all are based on the actual manufacturing cost of the parts.
Do you understand my point? The iCE40 devices are opening a new market for FPGAs that Xilinx and Altera can't currently fill. I think it will be interesting to see how this plays out. I think it will be similar to the tablet/smart phone vs the PC battle going on. The market for conventional FPGAs is much higher dollar at the moment, but the market for low power, mobile apps is huge and will eventually overtake the traditional FPGA markets. The question is just how soon?
It would be nice if you could trim your posts sometimes.
Rick
At a guess, differentiate the waveform to make it piecewise constant, integrate each piece, add the pieces, and integrate again.
Cheers
Phil Hobbs
Almost. From vague memory, you differentiate down to impulses, which are located via amplitude and an e^(-j*Omega*tau) term, convert those to sinusoids and you have the transform... used to be lightning quick when I used it regularly ;-) ...Jim Thompson
I raised the input voltage to the op-amp until it hit the rails. It became a clipped triangle as described. The harmonics went to hell in a hand basket.
/
Yeah. That looks nice, are those numbers from a soldered (vs simmed) circuit? In 'theory' you should be able to get rid of the even harmonics. So you are just clipping with the supply rails. To get rid of the even's that's either a pot or another opamp. I've read this nice paper on bounding and clamping by B. Pease. All sorts of clever diode bridges, I recall one that used a zener inside a diode bridge (or ring?) that used one zener for both sides.
We could always ask Jim T. how he did it. Say, How'd ya cut the tops off the triangle wave Jim?
Of course you've got to make the triangle wave too. (I've done the Volatge->R into integrator once. I got greedy and made the input resistor too big (input current too low) and found all sorts of sneaky current leakage.)
George H.
Yes, I mentioned the CPLDs above, but they are CPLDs and have very small capacities and very high prices relatively. For the same cost as around
64 CPLD macrocells you can get over 1200 LUTs and FFs, 64 kbits of RAM, up to 95 I/Os, 12 differential inputs and a PLL. They are also very old technology at this point.Rick
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Keep it all balanced (DC and slope wise) and at some gain the third harmonic should go through a minimum.
George H.
No, it's not. "Low power" is a design parameter.
I didn't ask for a product brochure. I can look them up myself.
Wrong. The only factor in the book price is "what the market will bear". If you think there is any relationship between manufacturing cost and book cost (other than a 'Do you understand my point?
That you're infatuated with Lattice? Sure.
I don't think it's going to succeed. That's not the market for programmable logic; too expensive.
Buy a scroll wheel.
get away
This modem
So being non-standard came back to bite you in the ass.
?-)
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