It's not just the XOR asymmetry, it's any delay asymmetry in the buffers that generate the delay. Tpd_lh and Tpd_hl are usually different, and logic thresholds aren't exactly Vcc/2. The OP did say he wanted his pulses to be precise.
Just use an AND or NOR gate, and use only one of the incoming edges, and avoid the hazard.
The dual one-shot thing is cleaner and easier to tune.
-- John Larkin Highland Technology, Inc jlarkin at highlandtechnology dot com http://www.highlandtechnology.com Precision electronic instrumentation Picosecond-resolution Digital Delay and Pulse generators Custom laser drivers and controllers Photonics and fiberoptic TTL data links VME thermocouple, LVDT, synchro acquisition and simulation
Not with a delay of only 10ns they're not.
But indeed NAND or NOR, one input direct from the 500ms timer, and the other input delayed by 10ns will do the trick. ...Jim Thompson
--
| James E.Thompson, CTO | mens |
| Analog Innovations, Inc. | et |
| Analog/Mixed-Signal ASIC's and Discrete Systems | manus |
| Phoenix, Arizona 85048 Skype: Contacts Only | |
| Voice:(480)460-2350 Fax: Available upon request | Brass Rat |
| E-mail Icon at http://www.analog-innovations.com | 1962 |
I love to cook with wine. Sometimes I even put it in the food.
The OP wants it adjustable from 10 to 250 ns.
This one goes from 100 ps to 25 ns:
-- John Larkin Highland Technology, Inc jlarkin at highlandtechnology dot com http://www.highlandtechnology.com Precision electronic instrumentation Picosecond-resolution Digital Delay and Pulse generators Custom laser drivers and controllers Photonics and fiberoptic TTL data links VME thermocouple, LVDT, synchro acquisition and simulation
And you are claiming you made it from 123's ?:-)
Give me a break, the 123 one-shot is one of the worst chip designs ever. ...Jim Thompson
--
| James E.Thompson, CTO | mens |
| Analog Innovations, Inc. | et |
| Analog/Mixed-Signal ASIC's and Discrete Systems | manus |
| Phoenix, Arizona 85048 Skype: Contacts Only | |
| Voice:(480)460-2350 Fax: Available upon request | Brass Rat |
| E-mail Icon at http://www.analog-innovations.com | 1962 |
I love to cook with wine. Sometimes I even put it in the food.
The OP has not define the resolution !
10 - 250 ns in 1 ns steps or 10 - 250 ns in 10 ns steps or 10 - 250 ns in xx ns steps ???Also, did the OP state how the control would be handled.
A carbon pot on a (xxx) analog timer chip would be all over the map and add offsets over temp.
What a mess !
If the OP is still around, what do you have in mind here ??
hamilton
Don't know if PICs have that, however a TMS28xxx high resolution PWM would be absolutely the simplest and the cleanest way to generate any pulse with
180ps timing resolution.Vladimir Vassilevsky DSP and Mixed Signal Consultant
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Are there any better ones? I've got some 74LS221's left over from an old insturment. (not very fast)
I really would like a fast double pulser, with variable delay.
George H.
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The 74HC4538 is better than the 123's or 221's but still not fast enough for a 10ns (stable) pulse width.
I go with NAND-ing a signal and a delayed replica. Varying the delay to adjust the pulsewidth. ...Jim Thompson
--
| James E.Thompson, CTO | mens |
| Analog Innovations, Inc. | et |
| Analog/Mixed-Signal ASIC's and Discrete Systems | manus |
| Phoenix, Arizona 85048 Skype: Contacts Only | |
| Voice:(480)460-2350 Fax: Available upon request | Brass Rat |
| E-mail Icon at http://www.analog-innovations.com | 1962 |
I love to cook with wine. Sometimes I even put it in the food.
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Thanks I'll give it a 'look see'. I don't really care about stable. (I want to simulate PMT pulses.)
George H.
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Dammit, stop making sense! I'm with Jim on this one.
One shots in general are a bad idea. I went through great pains on a multi-person design to use a counter to get around the one shot, only to find in a power down mode the crystal was turned off. Fortunately, other mistakes were in the chip so it wasn't like my screw up solely was to blame for blowing up the design budget.
The trouble with one shots is they can be influenced by power supply noise, temperature to some extend if gate delays are part of the equation, etc. By the time you design a one shot as good as a Swiss watch, it ends up being an analog beast.
Use the 555 to drive a one-transistor one-shot..
Sounds like you should have used a one-shot.
An HC123 isn't bad at all. It's fairly insensitive to Vcc and temperature.
There are some newer, faster parts, like SN74LVC1G123.
You can spend 10x as much (or, in my case, 200x as much) to make a faster, more precise pulse generator. Do that if you need to.
-- John Larkin Highland Technology Inc www.highlandtechnology.com jlarkin at highlandtechnology dot com Precision electronic instrumentation Picosecond-resolution Digital Delay and Pulse generators Custom timing and laser controllers Photonics and fiberoptic TTL data links VME analog, thermocouple, LVDT, synchro, tachometer Multichannel arbitrary waveform generators
-- Yes, but he also said that the period between pulses was non-critical, so that leaves only the pulse widths to contend with. Then, since the inputs aren't hysteretic, the assumption is that the high-going and low-going switching points will be equal, and if Tpd_lh and Tpd_hl are equal, the output pulsewidths will be equal for both the rising and falling edges of the exor inputs. See: http://www.ti.com/lit/ds/symlink/sn74ahc86.pdf >Just use an AND or NOR gate, and use only one of the incoming edges, >and avoid the hazard. > >The dual one-shot thing is cleaner and easier to tune.
Make that assumption if you want to, but it's usually not true. Actual CMOS input transition points are typically a bit below Vcc/2, but aren't guaranteed. And rising/falling edge prop delays are usually not the same. PFETS and NFETS are different animals.
Why create a bunch of hazards when it's completely unnecessary?
I think so. The XOR+delay requires a tunable delay that has a 25:1 spread. If you do that with an RC as you suggest, the edges get very slow for the longer delays; look at the input transition rate spec in the data sheet that you provided the link to. A dual one-shot gives you two clean, fast pulses to work with, and the tunable one only has to be varied over a fairly small range, like 110 to 350 ns maybe.
-- John Larkin Highland Technology Inc www.highlandtechnology.com jlarkin at highlandtechnology dot com Precision electronic instrumentation Picosecond-resolution Digital Delay and Pulse generators Custom timing and laser controllers Photonics and fiberoptic TTL data links VME analog, thermocouple, LVDT, synchro, tachometer Multichannel arbitrary waveform generators
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nAn ON-Semiconductor MC100EP195
offers a digitally programmable delay from 2nsec to 12nsec. You can run the same pulse through one or - maybe easier - two of these parts under the control of a programmable counter until you've built up the
20 to 250nsec of delay the OP is asking for, and then release the timing pulse after that delay.More complex than a monostable, and the propagation delay through the MC100EP195 is depressingly temperature dependent - the maximum delay increases by 6% from 25C to 85C and is decreased in the same proportion at -40C, and the minimum delay changes about twice as fast, but it might be good enough for use in an air-conditioned lab.
On the other hand, it's ECL so the power rails will be clean and the edge transitions quick - about 100psec. You've got to route your logic along traces that look like terminated transmission, but at least ECL is designed to drive terminated connections.
It would make an odd mix with a 555, but this may be one of those rare occasions where a 555 is the easiest quick and dirty option - albeit it very dirty.
-- Bill Sloman, Nijmegen
a cpld, 10 lines of verilog and a 100MHz oscillator, something like xc9536xl for example
26bit counter to give you ~2Hz, 5 bit counter to give you 10 to 310ns pulse in 10ns stepsif you want pulse lengths that are not a multiple of 10ns, use a different oscillator
-Lasse
The dual 123 plus one gate package - two cheap cans - clearly wins over the ECL idea.
The Micrel delay line chips (SY89xxx) are better than the Onsemi ones, but still not a very good way to do this.
This would work, for both the 2 Hz ticker and the pulse generator:
-- John Larkin Highland Technology Inc www.highlandtechnology.com jlarkin at highlandtechnology dot com Precision electronic instrumentation Picosecond-resolution Digital Delay and Pulse generators Custom timing and laser controllers Photonics and fiberoptic TTL data links VME analog, thermocouple, LVDT, synchro, tachometer Multichannel arbitrary waveform generators
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, hAnd a 221 beats a dual 123 in any application where you don't need to retrigger the monostable. As Jim Thompson pointed out, the 123 is crummy monstable. He didn't bother to point out that 121 is a whole lot better if you don't need to retrigger.
The advantage of the ECL part lies in the quality of the pulse edges it generates, and the stab\ility of the delay, particularly against power rail noise. The 121 and 123 are essentially analog comparators looking at a relatively slow ramp. Any noise on the ramp or the voltage the comparator is using as a reference create a lot more jitter than the same power rail noise would create in the ECL system, and the power rails in an ECL system are pretty much guaranteed quieter than the power rails in a TTL system.
And the ECL system does lend itself to self-calibration schemes, where you calibrate the delay generating engine from time to time by getting it to produce a pulse-width modulated waveform, where the repeat time is controlled by a much more stable clock - which could be derived from an off-air standard, traceable back to something at the local National Bureau Standards.
Here you could go for a 3MHz repeat cycle and use the delay engine to vary the high time from say 35nsec to 285nsec. Digitise the filtered DC content of the waveform and you've calibrated the delay engine against the 3MHz clock.
In practice you'd derive the 3MHz clock from a good 10MHz clock and generate two additional 135nsec and 235nsec "high" period waveforms by adding in one or two periods of the 10MHz clock, allowing you to interpolate between exactly known PWM waveforms and the waveforms being calibrated.
You can find and calculate out more subtle errors by repeating the procedure with slower clocks - say 2.5MHz and 2MHz.
It would be a whole lot better way - if more expensive and complicated
- if you designed it right.
Perhaps. Does it do any self-calibration? TTL is a a bit of a problem if you are serious about getting accurate low-jitter timing signals.
-- Bill Sloman, Nijmegen
This is the way I generate precise delays (on-chip)...
This delayed signal is then used to create non-overlapping drives for such things as full-H bridges, and commutating switches used in synchronous rectification and integrate control loops.
Analysis is left as an exercise for the student ;-)
Hints:
(1) These are 10ps inverters (TSMC 0.18u process) (2) This is internal to a monolithic chip, so no ESD to get in your way, so left end of the cap flys above VDDD and below GNDD without clamping or consequence.
This snap-shot is from a chip I designed last fall when I did an extended stay (:-) on Long Island and met Martin Riddle.
Designed entirely on my laptop, the chip worked perfectly to specifications first pass thru the foundry, as do ALL of my designs... I never do "designs" without component values >:-) ...Jim Thompson
--
| James E.Thompson, CTO | mens |
| Analog Innovations, Inc. | et |
| Analog/Mixed-Signal ASIC's and Discrete Systems | manus |
| Phoenix, Arizona 85048 Skype: Contacts Only | |
| Voice:(480)460-2350 Fax: Available upon request | Brass Rat |
| E-mail Icon at http://www.analog-innovations.com | 1962 |
I love to cook with wine. Sometimes I even put it in the food.
It does some self-cals, but all timings are based on a crystal oscillator, a TCXO, so are very stable. There are tempco corrections, so TC is typically in the few-ps per degree C sort of range. The "TTL" output edges are around 650 ps rise/fall, faster than 10K ECL.
The OP could conceivable make a dual-one-shot thing himself, in a sensible amount of time. If that's not good enough, it would make sense to buy something, rather than spend weeks or months doing something based on ECL delay lines and supporting logic.
ps - I did design this myself, and I did write the embedded uP code. Somebody else did the FPGA code.
-- John Larkin Highland Technology, Inc jlarkin at highlandtechnology dot com http://www.highlandtechnology.com Precision electronic instrumentation Picosecond-resolution Digital Delay and Pulse generators Custom laser drivers and controllers Photonics and fiberoptic TTL data links VME thermocouple, LVDT, synchro acquisition and simulation
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