I have a simple program that runs the (timer2) PWM reliably, scope measurements confirm timing of pulse width and the rate as well. I add a simple 256 location lookup table to change the PW on a cyclic basis. Still OK but not exactly verified with scope on a dynamic basis, tho verified that i get the proper PW at setting of CCPR1L.
Now, here is when i get into trouble; adding an interrupt.
Number one: exactly when is that interrupt hit, at end of the period, or at end of the pulse? (note if CCPR1L=0 there ain't no pulse, at one it is 200nSec and at 255 the low time is 200nSec)?
Number two: exactly what code and what order is required for reset before i kick it back on with BCF PIR1,TMR2IF and BSF INTCON,GIE?
The simulator is of no help (for me). I do know that i better have all instructions execute from reset until i kick on the interrupt (or i am really SOL).
Without looking at the data sheet, the interrupt occurs at the end of the period when teh counter rolls over eg 0x0000. The data sheet usually says to clear the IF.
That may be true for 8 bit PWM. 100% duty cycle occurs when the duty cycle is set greater than the PWM period. The period is [(PR2)+1] * 4 * Tosc * (Timer2 Prescale). The PWM value is 10 bits with a maximum value of 1023. It may be possible to set the period longer than the maximum PWM duty cycle time such that maximum duty cycle is less than 100%, but I'm not sure about that.
I would suggest reading some of the application notes that describe the process, such as:
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AFAIK, the interrupt occurs when Timer2 matches the value of PR2. This occurs at the end of the PWM period and the start of the next cycle. This will occur even at duty cycles of 0% and 100%. You can use this interrupt to change the value of CCPR1L and CCP1CON for 10 bit resolution. This PWM value will be used for the next PWM period.
The CCP interrupts (CCP1IF or CCP2IF) are not used in PWM mode.
See below, from the linked document.
You can use the logic analyzer to see the PWM on the appropriate pin(s).
Mostly you need to make sure all the outputs and inputs are initialized to a "safe" mode. I/O pins are tri-state at power-up so it is important to have pull-ups or pull-downs to avoid undefined floating voltages, especially when driving MOSFETs or logic or analog devices with high-impedance inputs.
CLRF CCP1CON ; CCP Module is off CLRF TMR2 ; Clear Timer2 MOVLW 0x7F ; MOVWF PR2 ; MOVLW 0x1F ; MOVWF CCPR1L ; Duty Cycle is 25% of PWM Period CLRF INTCON ; Disable interrupts and clear T0IF BSF STATUS, RP0 ; Bank1 BCF TRISC, PWM1 ; Make pin output CLRF PIE1 ; Disable peripheral interrupts BCF STATUS, RP0 ; Bank0 CLRF PIR1 ; Clear peripheral interrupts Flags MOVLW 0x2C ; PWM mode, 2 LSbs of Duty cycle = 10 MOVWF CCP1CON ; BSF T2CON, TMR2ON ; Timer2 starts to increment ; ; The CCP1 interrupt is disabled, ; do polling on the TMR2 Interrupt flag bit ; PWM_Period_Match BTFSS PIR1, TMR2IF GOTO PWM_Period_Match ; ; Update this PWM period and the following PWM Duty cycle ; BCF PIR1, TMR2IF
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