Yes. We couldn't compare the FPGA to an external delay line (they aren't very good) so we'd need a clever (and affordable) way to compare a prop delay to a clock.
Of course, every time you compile an FPGA design it may change the routing radically.
Sometimes the optimizer decides that you really don't need to do something at all.
But amusing is the enemy of cheap and done. That's a real problem in this industry.
John Larkin Highland Tech Glen Canyon Design Center Lunatic Fringe Electronics
You're no fun anymore. ;)
Cheers
Phil Hobbs
You're no fun anymore. ;)
Cheers
Phil Hobbs
Am 24.02.26 um 04:16 schrieb john larkin:
I've built a switchable delay line from a reel of semi rigid coax, heaps of SMA connectors and 3 pairs/stages of 1-to-6 coax relays. The 1-to-6 relays were surprisingly cheap at ham radio meetings, there exist not many apps for them.
The delay line could bring anything between 4 and 100 MHz into phase quadrature for phase noise measurements. It was a lot of work soldering SMAs, verifying / trimming cable lengths on the TDR and packing everything into a 19" crate.
Exactly when I was done, I got hold of a Time Pod that could do everything with 20 dB better pn resolution thanks to cross correlation.
Back in Xilinx XC3020 times, a friend did his FPGA design barefoot with the XACT editor by hand and he locked down every connection and transmission gate. He ran out of luck when the next chip delivery showed better but different timings.
He is a chip broker now.
Cheers, Gerhard
There are some SMT 90-cent DPDT relays that are pretty good up to around 5 GHz. One could make a switchable delay line from them.
The challenge would be to get lots of bits with monotonic - or even calibrated - delay.
John Larkin Highland Tech Glen Canyon Design Center Lunatic Fringe Electronics
The classical 1970s preregulator design should do it if you're contemplating using the 337 on the basis of 317 PSRR specs. That would be using the final output as the input to the ADJ on the pre-reg. You should be able to get away with 3 Volt headroom, a bit more than the stock 1.5V.
On 2026-02-24 15:00, Someone wrote:> The classical 1970s preregulator design should do it if you're > contemplating using the 337 on the basis of 317 PSRR specs. That would > be using the final output as the input to the ADJ on the pre-reg. You > should be able to get away with 3 Volt headroom, a bit more than the > stock 1.5V. >
Thanks. Unfortunately I'd need three LM337s to get the sort of PSR required. :(
They really stink.
The LCR filter plus shunt-regulator-supervised cap multiplier is the fallback position if the TCA0372's negative-supply rejection isn't up to the job. (I need to measure that tomorrow.)
Cheers
Phil Hobbs
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