Fet G-S zener

You mean besides the obvious ones (conduction current, blocking leakage..)?

Capacitance I guess, which can lead to gate oscillations, especially on modern FETs (SuperJunction) which like to sing at 300-400MHz (where even a

Tim

Right, thanks. like capacitance. So a little through hole, 1/4 W, 1n5xxx is about 20 pF on our lcr bridge. That seems about right.

George H.

Capacitance. I like to use the CB junction of a BFT25A between the gate and some reference voltage. (Keeping CPH3910s alive when connected to APDs running at -220V, for instance.)

Cheers

Phil Hobbs

Right, I think I can live with 20 pF more.

But this CB junction thing. So I do have an N-Fet, I then drew the collector (of npn) attached to the gate, base to source... which leaves the emitter flapping around. I don't see how attaching the emitter to some reference V causes anything to turn on? Does the BFT25A have some predicable (lowish) Vcb?

George H.

There are lots of fets with internal g-s zeners. They tend to conduct around 40 volts. You might have to limit the current; a resistor or parallel RC would work.

George, I believe Phil was referring to the use of the CB junction as a low leakage, low capacitance diode. the emitter is left floating. there was a discussion about this a few months back, the thread title is "JFET used as a diode"

Oh, that makes much more sense, thanks! George H.

(Assuming you wrote about a MOSFET rather than a JFET then) Strictly speaking you didn't blow the "junction" because a mosfet gate has no junction, what happened was you broke down the gate insulation dielectric material.

I think John Larkin reported that +/-20Vgs rated parts typically ruptured above 70V.

piglet

Yes, sorry--I thought I'd expanded on this in another post, but it hasn't appeared.

The CPH3910 JFET has a maximum V_GS of -15V. In my recent APD front end, I use a BAV99 series-connected dual diode with the anode connected to the source, the midpoint connected via a resistor to -5V, and the cathode connected via a BFT25A C-B junction to the gate. That bootstraps the already small capacitance and reduces the leakage to femtoamp levels.

The reason for doing it is if somebody opens up the instrument with the APD bias attached, the gate of the FET would get pulled away towards

-220V. The APD bias is current-limited to a few hundred microamps, so this is a complete solution.

Cheers

Phil Hobbs

Right, I blew out the gate and maybe made a junction. I'm not sure exactly how much overvoltage, but a quick calc would say 5 x 15V.. ~70V. (STN4NF20L) I'm not going to repeat the experiment... only 4 pieces left. :^)

George H.