annular rings in vias

IPC allows reduction in annular rings if the process has been vetted prior to fab. You might be aware that annular rings are evaluated after all etchback and drilling fab stages - they are not what appears in the artwork....

RL

I take it there's some reason why you can't put a little bridge of ribbon cable on the other side to the connector.

NT

The package we are (mostly) currently using - KiCad - does not include "pad stacks", which are used to encode the pad diameters on a per-layer basis :( Mostly it's excellent, but that's a serious deficiency. {It's possible there's a bleeding-edge version that has it; I'm currently using 4.0.5.}

The feature of omitting pads on inner layers when not used is a separate issue. I believe what you are describing allows different sizes and shapes of pads on different layers. But normally if you don't want pads on inner layers when not used, that can be accommodated.

Den onsdag den 11. oktober 2017 kl. 22.22.55 UTC+2 skrev John Larkin:

Yeh, doing it in the gerbers won't give you the routing space unless you ignore DRC errors

anyway, for routing a fine pitch BGA every mil counts, but is it worth hassle for big power connections? all you gain is the minimum annular ring maybe 4-5mil

Perhaps I'm missing something obvious - but how? I found a discussion from a few years ago where someone was generating a custom via/pad which had these properties, but other than this nothing... I'd be grateful if you could tell how this might be accomplished.

What Bill Birch doesn't seem to mention is that the formation of barrel cracks in vias is usually associated with thermal stress. The greatest stress in the life of the board will occur in fab - lead-free reflow - and so is detectable at early stages of product development.

That's what the process vetting mentioned in IPC implies, for this specific issue.

RL

One recommendation on IPC TechNet was to try to retain the annular ring in alternate layers. This could free up the specific layer you're tracking through, while maintaining the via barrel's integrity through the stack.

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Allegro has long had the ability to "suppress unconnected pads" at artwork generation time; however, it now has functionality to do it dynamically, du ring routing, so you can route closer to plated through holes, without need ing to make a custom pad stack.

I did a layout with a DVI video connector, which has pins three ranks deep. I needed to route diff pairs on three layers. The pads were so close tog ether that constraints would not allow me to route between them unless I ed ited the pad stacks and removed the unwanted annular rings. I haven't trie d it; but I believe Allegro 17.2 can remove unused pads as you route.

Through-holes that carry hardware have different issues, though the density of some of these must make tracking signal integrity a real headache. Selective removal of annular rings would be least risk.

I wouldn't trust the software to make that decision - it should be a conscious edit.

RL

I'm not sure what you are asking. This is a function of the CAD package you are using. The package I used allowed the inner pads to be removed if not used either on a pad stack basis or for the whole board. What layout software do you use?

As I stated initially, I had a complaint specific to the otherwise very good 'kicad' (pcbnew) package. I presumed that you had discovered a way to make this package perform in ways not known to me (and others). Oh well.

No, I haven't used KiCad as yet. Good to know one of the potentially more likely to bite me issues...