ADUC7020

Is there anyone here who knows all about the ADUC7020?

I'm about to give up on getting an answer from Analog.

There is one line in the whole data sheet that makes me believe that you can make the DACs update on a reload of Timer1 but nothing about the specific timing or any details.

Does anyone know?

Reply to
MooseFET
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Hey, I don't want to hear about your problems... I'm trying to get an answer from Analog Devices about the AD7699! I think I have finally got them to admit that reference drift does *not* explain zero offset TC.

The interfaces and datasheets of mixed-signal products are typically horrible.

John

Reply to
John Larkin

Oh-oh. Guess who else had looked at that datasheet.

Lucky me, I had already decided "perhaps not" If I have to use just an ARM with external converters, odds are I'd go with Linear's converters. I had been looking at the AD 8 channel DAC and a

14 bit ADC.

This is one place where the folks at Silabs do a fairly good job. They document the analog parts as though they were external things. It is like they get the guy who does the analog section to write up something that goes to the technical writers.

Reply to
MooseFET

Hmm. A customer of mine is planning to use that part to digitize very low frequency stuff--seismometer and tiltmeter data and so on...could you say a bit more about what the issues are?

CCD chips are the worst, IME.

Cheers

Phil Hobbs

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Dr Philip C D Hobbs
Principal
ElectroOptical Innovations
55 Orchard Rd
Briarcliff Manor NY 10510
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hobbs at electrooptical dot net
http://electrooptical.net
Reply to
Phil Hobbs

I am seeing a huge amount of zero drift with temperature. Chris Augusta, the guy at ADI who wrote the datasheet, helped me find the problem. I now owe him beers.

In bipolar mode, you apply a differential input between a pair of pins, like IN0 and IN1, pins 16 and 17, for instance. Turns out that the IN1 pin must be within +-0.1 volts of Vref/2 or the zero TC goes to hell. It says that on the datasheet, but I missed it somehow. I'd got too used to pseudo-differential charge-balance ADCs actually having lots of common-mode rejection. My bad, I guess.

On my board, I'm using a 2.5 volt bandgap and a C-load follower opamp to generate the Vcm used by all 16 ADCs. I can change that to a 2.048 bandgap and get legal again.

Here's the board:

formatting link

Now I can crank the accuracy specs up to less embarassing numbers.

John

Reply to
John Larkin

Oh, if they plan to run this ADC at 500 KHz, the timing is right on the bleeding edge. Rob has working VHDL if anybody needs it.

John

Reply to
John Larkin

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