RS Components have just hosted images of a board marked "Raspberry Pi 2 v1.1", then took them down again.
Rumours about this suggest that it's either a new board with a faster CPU or that these were just images of a B+ prototype.
Somebody grabbed the images before RS took them down:
Well, the current model B+ is v1.2, whereas the image claims v1.1. The image is not quite the same as a current v1.2.
Also, it's showing a broadcom chip with no memory piggy-backed on it, and an extra chip on the reverse, which is presumably the memory.
I never saw a model B+ v1.1 (was it ever released?), but I'm guessing these are just old images.
-- Andrew Gabriel [email address is not usable -- followup in the newsgroup]
Yes, I agree.
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Well, those are the same pictures as captured earlier.
Increasing to 1Gb could be the reason for moving the RAM to the board back rather than piggy-backed on the processor. Still has a version on the silkscreen which is older than the current B+ though. Maybe its design predates the current B+?
One of the original reasons given for using only 512MB RAM was that no one made a 1GB RAM chip in the right format. Presumably the Pi numbers shipping have made that worthwhile doing now.
Anyway, good news.
-- Andrew Gabriel [email address is not usable -- followup in the newsgroup]
Indeed!
It's essentially the same SoC with a diferent CPU core (or cores as there's now 4 of them). The memory is faster too, so overall it's actually a very usable little computer now - perfectly usable as a day-to-day workstation.
I was lucky to get one a few days ago so I could update my wiringPi libraries for it - quick overview here:
Gordon
Did you get a chance to measure power consumption? I would be interested in how much more current it requires compared to the B+.
TIA, Paul
Interesting, thanks. I currently use the filesystem interface to the GPIO pins (horrible though it is), so the change in base address won't impact me. (I did initially start by memory mapping the gpio which gives you access to things not implemented in the filesystem interface, but I haven't used that for a while.) The only change I have to cope with in my code are a couple of the GPIO numbers which changed after the first rev of the board.
-- Andrew Gabriel [email address is not usable -- followup in the newsgroup]
Not yet. Not sure I have the cabling to do that right now, but I'll see if I have time to cobble something up later on.
Gordon
Gordon, did they send you a hardware spec document, or just tell you 'the GPIO is over there'? I'm interested in using some of the Cortex A7 features but I need some hardware information - for the original Pi this trickled out some months after release, so just curious if there is official documentation ready to go?
Ordered one. Interesting to watch the stock levels at Farnell falling in real time ;-)
Theo
Just ordered one, but I promise not to put Windows 10 on it.
-- Andrew Gabriel [email address is not usable -- followup in the newsgroup]
Do you know whether the Python bindings need to be/are being updated?
The hardware spec is the same as the Pi v1 - it's virtually the same SoC with a different CPU core. The A7 side should be the same as any other A7. (but that's not my area of expertiese - I haven't looked at ARMs at the architecture level since the days of the Archimedes...)
All I've done is detect the version of Pi and adjust the GPIO peripherals base accordingly.
Gordon
I understand Ben Croston got one before release too, so I imagine there will be a new RPi.GPIO pushed out via the repository soon - if it's not already in the works.
Gordon
has anyone tried it with raspbmc/kodi yet? I may end upo with a 3rd pi now (I suppose I could give 1 to my son )
-- I'm reporting for duty as a modern person. I want to do the Latin Hustle now!
Thanks, but I actually meant the python bindings for wiringPi2. I realise that's not strictly your work, but wondered whether you had any info. Thanks, Tony
Oh, sorry. I've no idea. Best get in-touch with Phil/Gadgetoid there...
Gordon
The questions are things about eg bootloader arrangements, memory map etc. For instance, does the GPU do any multicore bringup (setting up cache coherency), or does it just put some stuff in RAM and turn on the ARM? There's numerous things that would be caused by changing from a single core to multicore world. Likewise, is the USB part the same or did it get fixed up to be less painful? It obvious isn't a near-identical SoC if something as basic as the GPIO moved.
This would be covered in a hardware specification document, which is why I was enquiring if you'd seen such a thing.
I note patches for bcm2709 have been committed to the kernel today - dating back to May 2013 - so I'm having a stare at those. The Device Tree looks useful.
Theo
I'm pretty sure it's the same USB, but as for the rest...
might be useful?
Nope.
The DT stuff is enabled by default in later Pi kernels now. (not yet the released kernel for the Pi v2 AIUI)
Gordon
Bit the bullet anyway so I guess I will find out soon enough :-) Glad the MPeg Licence was not expensive.
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