Discreet component monostabe constructed from a =91TTL=92 OR gate , resistor and capacitor , Im trying to determine what the pulse width should be from the timing components, but I don=92t see any info on this configuration. I need to certify the cct is in specification .. Its fed with a 0 > 5v step
From a common start point, one line direct to gate (1) input, from the same common start point, a 220 ohm resistor connected to the second gate (2) input.
From the junction of the 220 ohm resistor and the second gate input is connected a 0.0022nF capacitor to ground.
The resistor and capacitor form a cr timing network.
Operation appears to be , the initial 'ON' voltage (5v) is applied direct to gate (1) , the capacitor to ground delays the voltage applied to gate (2) charging via the 220 resistor.
When the two inputs are at logic =911=92 then the =91OR=92 Fnction changes = the gate state .
Im seeing a 650nS pulse , has anyone a formula or a chart that gives a guide to pulse duration ?