Hi all, ! As the tile says, I'm into reverse-engineering secured PLD in these days. Until now I've used with success the this PAL dumper:
It works most of time but it supports PLD devices up to 20-pin.Now I'd want to reverse secured combinatorial (registered ones are really hard..) 24-pin PLDs (like PALCE20V8H) which often I encounter on my PCBs. What would be your approach to this aim?Recreate equations by studiying PCB connections?Or brute-forcing the device trying all possible input combinations and logging the outputs (this is what the PAL dumper does, I presume)? My EPROM programmer has a vector test feature, maybe it could be useful in conjunction with the use of a logic analyzer? Besides, I came across this page where a guy clones some PAL using a simple device he built but also this support PLDs up to 20-pin:
Do you think it could be easily adapted in order to dump 24-pin PLDs? I hope someone can help me. Thanks in advance