Hi All,
I'm experiencing problems with CCS C 3.224 and slave I2C.
Sending data from master to slave works without problems, but when I try to read data from the slave then the data becomes corrupt. (The master receives the data right shifted one bit so if I send 0xCC the master receives 0x66, if I send 0x80 then 0x40 is received etc)
The code is based on Application Note 734 with state 5 logic and i2c_write code fixed according to other peoples examples on the 'net.
CODE (all non-I2C code is removed for clarity)
#include #device *=16 #device adc=8 #fuses HS,NOWDT,NOPROTECT,NOLVP,NODEBUG,PUT,NOBROWNOUT #use delay(clock=20000000) #use i2c(SLAVE, SDA=PIN_C4, SCL=PIN_C3, address=0x44, FORCE_HW, SLOW)
#byte SSPBUF_REG = 0x13
#bit SSPCON_CKP = 0x14.4 #bit SSPCON_SSPOV = 0x14.6 #bit SSPCON_WCOL = 0x14.7
#byte SSPSTAT_REG = 0x94 #bit SSPSTAT_BF = 0x94.0
typedef unsigned char Uint8_t;
void i2c_write_ex(Uint8_t data) { // Wait until buffer empty while (SSPSTAT_BF) ;
do { SSPCON_WCOL = 0; SSPBUF_REG = data; } while (SSPCON_WCOL);
SSPCON_CKP = 1; // Release clock }
#INT_SSP void i2c_isr() { Uint8_t tmp; Uint8_t status; status = SSPSTAT_REG;
switch (status & 0b00101101) { case 0b00001001: // Master write address (State1) tmp = SSPBUF_REG; // Read address and throw away break; case 0b00101001: // Master write data (State2) tmp = SSPBUF_REG; break; case 0b00001100: // Master read (address byte) (State3) case 0b00101100: // Master read (data byte) (State4) i2c_write_ex(0xCC); break; case 0b00101000: // Master NAK (State5) SSPCON_CKP = 1; break; default: // Error reset_cpu(); break; } if (SSPCON_SSPOV) { SSPCON_SSPOV = 0; // Reset overflow tmp = SSPBUF_REG; } }
void main() { enable_interrupts(INT_SSP); enable_interrupts(GLOBAL);
for (;;) { } }