external memory problem

Do you have a question? Post it now! No Registration Necessary

Translate This Thread From English to

Threaded View


I am using a 89C450MCL mcu running at 29.492mhz
With just the micro, 74F573 (or 74HCT573 tried both) and a IS62C1024-35 RAM
chip it seems I loose the address sometimes at the output of the latch when
/WR goes low.
I am using plenty of bypas caps and 4.6uf caps for supply lines.
I am simply trying to clear a memory range from 0000h - 00FFh.
I put my logic probe on the address lines of the RAM chip after the latch
and I can see the address sometimes going wrong.
See
http://www.eddie1.net/timing.jpgfor reference.
As you can see I am just writing to memory and as the image shows 1Ch is
fine 1Dh is fine but 1Eh and 1Fh are dropping the address then 20h is fine
and 21h is fine.
This is not the only place it goes wrong and I cannot find any corelation in
the locations that go wrong.
Any ideas??



Re: external memory problem


Not that I know the RAM, but it seems as if you might mix a TTL level
device (both 74F573 and 74HCT573) with a CMOS device (IS62C1024-35)
Look at the requirements for a HI input of the RAM and see if the TTL
device will garantee that high voltage.
Your logic probe does _not_ measure the exact voltage !
If that is causing the problem, you can "help" the TTL device by adding
pull-up resistors in the output of the TTL (input CMOS device)
That my idea
Cheers

Ed skrev:
Quoted text here. Click to load it

Re: external memory problem


Rubbish!
What I wrote was correct with the 74F device, but the 74HCT device
should make the correct output.
Then I would verify that the input on the xx573 also is latched to the
output of the device. If not use pull-up on the input of the 573! or at
least check the voltages during the latch pulse.
More Cheers

Klaus (DK) skrev:
Quoted text here. Click to load it

Re: external memory problem



Quoted text here. Click to load it
Do you have pull-ups on P0?????? ( not another one surely :)   )



Site Timeline