This may depend on the hardware you use, but the interrupt hardware unusually does not have a FIFO to store multiple interrupts.
When using shared interrupts, multiple hardware interrupt sources are routed to a single interrupt pin of the CPU or near-CPU interrupt controller.
AFAIK, this is not related to weather the pin the (external) hardware is connected to is programmed to detect a permanent level change (that needs do be reset by serving the external hardware by the software) or a pulse (that does not need a service to go on doing it's task and perhaps create another pulse).
So the difference between level triggering and edge triggering is that with level triggering in fact an interrupt will not be lost undetected, but instead the hardware will fail to do it's next task if the CPU is not able to service an interrupt fast enough.
In both cases the CPU failing to service the interrupt fast enough will result in loosing a hardware event, unless the event itself can be delayed by the hardware (if level triggering is used and the hardware is done in the appropriate way).
-Michael