I use two USARTs on AT91RM9200 (running linux built by Buildroot) to send and receive data packets of variable length (typical 513 bytes). Each USART is set to 485 mode and baud rate is 250K. Between the data packets is a break of approximately 112 microseconds. USART is set to interrupt on receiving breaks. DMA is used for data transfer. When USART interrupts on receiving a break (RXBRK), the interrupt service routine (ISR) reads DMA data counter to mark the beginning of a new packet in the DMA buffer, and then transfers the data of the packet just received from DMA buffer to device buffer.
The problem I have now is that from time to time when RXBRK interrupt comes and the ISR reads DMA counter ATMEL_PDC_RCR, the counter value is already 1 byte beyond the beginning of the packet. It looks like the RXBRK interrupt is not serviced quickly enough and the DMA already transfer the byte following the break into the DMA buffer when the ISR is invoked.
Would you please give some pointers on what might cause the delay and how to correct it? Thank you!
Susan