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Re: One Second Pulse-Width, Once Per Hour

I can't locate the original post, but there was a request for a way to

> generate a one second pulse-width, occurring once per hour. I > happened on to a similar circuit in the 74HC4040 data sheet and > modified it for the required pulse-width. > > It is posted on the S.E.D/Schematic Page of my website as... > > "OneSecPulseWidthOncePerHour.pdf"

Aren't there 2 race conditions?

If the flipflop output drove the counter reset that would fix one. (Possible runt clock pulse.)

If the flipflop set and clear were used instead of the clock input that would fix the other. (Clock rises right after clear goes false.)

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Reply to
Tom Del Rosso
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Jim's circuit actually gives a one-second pulse every 30 minutes. That's because the high-order stage goes through only half a cycle; the 2^12 stage goes high after 2^11 seconds. The 2^5 connection is OK, but the three 2^10 to 2^12-stage connections must be incremented. Fortunately the necessary stages are available on the 4020 chip type.

The clock/reset pulse is about a dozen logic delays long, because of the ripple-counter's delays, so it will work in that respect.

However, I prefer synchronously clocking the output flipflop, which is more accurate (*exactly* 1 second) and reduces the IC count. A single octal logic gate (hc30 or cd4048) decodes the required 3599 count for the flipflop's D input, and no inverters are necessary.

Another pleasant choice is the elegant little RED3600 divider from LSI Computer: This means yet one fewer IC, and a miniDIP at that!

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Thanks, - Win

whill_at_picovolt-dot-com

Reply to
Winfield Hill

The critical timing parameters for this circuit are the minimum CP width and the CLR removal time for the 74HC74, and minimum MR width for the

4040. Minimum CP is on the order of the family gate delay, and the circuit maintains CP for three delays: HC4040 MR->Qn->HC20->HC04. The CLR removal time is the minimum time HC74 CLR must be removed to guarantee the FF will receive the CP clock positive edge- the requirement here is a very brief time 5ns, on the order of 1/3 gate delay. The circuit margin here is even greater, being the HC20 gate delay plus the HC4040 ripple counter delay from Q1 to the least bit detected by the HC20 which is about 4ns per stage. The minimum MR duration will be three gate delays: HC4040 MR->Qn, HC20, and HC04. So that overall, the worst-case timing margin is two macro gate delays, making allowance for worst case transition times on the order of a single gate delay. The circuit will work reliably under all environmental operating conditions.
Reply to
Fred Bloggs

The circuit decodes a 3600 count of 1Hz CLK- this is ONE hour. The timing is exactly synchronous with the negative going clock edge and the timing accuracy is within 50ppb.

Reply to
Fred Bloggs

Win, Your brain must be slipping. Time for some VetaVitaVegamin ?:-)

No.

81ns from clock edge to reset pulse.

20ns until reset is accomplished internal to the 4040.

Reset pulse is 46ns long.

"*exactly*" ???? Give me a break. But the measured one second in my circuit is just 53ns shy of an exact second in width; and occurs

*exactly* once per hour.

Everyone wants junk-box parts... I use junk-box parts and then you recommend a single-source specialty part ???

...Jim Thompson

--
|  James E.Thompson, P.E.                           |    mens     |
|  Analog Innovations, Inc.                         |     et      |
|  Analog/Mixed-Signal ASIC's and Discrete Systems  |    manus    |
|  Phoenix, Arizona            Voice:(480)460-2350  |             |
|  E-mail Address at Website     Fax:(480)460-2142  |  Brass Rat  |
|       http://www.analog-innovations.com           |    1962     |
             
I love to cook with wine.      Sometimes I even put it in the food.
Reply to
Jim Thompson

I read in sci.electronics.design that Jim Thompson wrote (in ) about 'One Second Pulse-Width, Once Per Hour', on Thu, 1 Apr

2004:

That's a whole 53 feet at the speed of light!

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Reply to
John Woodgate

IIRC (I can't seem to find the OP) the requirement was a one second pulse to drive a relay. I do think that a relay won't mind that it's

53ns short ;-)

...Jim Thompson

--
|  James E.Thompson, P.E.                           |    mens     |
|  Analog Innovations, Inc.                         |     et      |
|  Analog/Mixed-Signal ASIC's and Discrete Systems  |    manus    |
|  Phoenix, Arizona            Voice:(480)460-2350  |             |
|  E-mail Address at Website     Fax:(480)460-2142  |  Brass Rat  |
|       http://www.analog-innovations.com           |    1962     |
             
I love to cook with wine.      Sometimes I even put it in the food.
Reply to
Jim Thompson

That would be 53 feet out of 186,000 mile span?

Reply to
Fred Bloggs

That's not the point. The stuff switched by the relay might.

;-D

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Reply to
Chris Carlen

[snip]

Lame attempt at jocularity noted ;-)

...Jim Thompson

--
|  James E.Thompson, P.E.                           |    mens     |
|  Analog Innovations, Inc.                         |     et      |
|  Analog/Mixed-Signal ASIC's and Discrete Systems  |    manus    |
|  Phoenix, Arizona            Voice:(480)460-2350  |             |
|  E-mail Address at Website     Fax:(480)460-2142  |  Brass Rat  |
|       http://www.analog-innovations.com           |    1962     |
             
I love to cook with wine.      Sometimes I even put it in the food.
Reply to
Jim Thompson

Sheesh! You're right, I must be slipping, 2^11 = 2048, I knew that!

Certainly your pulse starts at 1-hour intervals, but it's the one- second duration that suffers. The ripple delay spec is 1160ns max for a CD4040 to Q5 (with 50pF load), and 63 + 4*38 = 215ns for an HC4040 (from the Motorola data sheet), compared to 63ns for the Q1 output delay. Sure 152ns max isn't much, but it's more than zero (i.e. equal delays hi- and lo-going) for my preferred synchronous connection. (I used to design battery-powered instruments where sub-microsecond cmos delays in this type of timing circuit *did* matter... hmm, that was in 1969, and no 'HC parts were available.)

Hey, what about my preferred synchronous connection also saving on the parts count, isn't that important anymore? Doesn't that count?

Yep, some junk boxes are better equipped than others - I have the cool RED60 and RED3600 parts in mine! Besides, I'm sure you don't mind my mentioning elegant exotic parts if they're reasonably easy to get: Gemini Electronic Components, Valhalla, NY (800) 882-6414.

Thanks, - Win

whill_at_picovolt-dot-com

Reply to
Winfield Hill

[snip]

Do you remember the VetaVitaVegamin skit that Lucille Ball did eons ago ?:-)

I personally wouldn't use the 4040, I'd use something in the 'HC160 family, but that requires thinking about pre-loading, etc., something I couldn't manage after a nice wine luncheon with my wife, celebrating our 44th Anniversary ;-)

...Jim Thompson

--
|  James E.Thompson, P.E.                           |    mens     |
|  Analog Innovations, Inc.                         |     et      |
|  Analog/Mixed-Signal ASIC's and Discrete Systems  |    manus    |
|  Phoenix, Arizona            Voice:(480)460-2350  |             |
|  E-mail Address at Website     Fax:(480)460-2142  |  Brass Rat  |
|       http://www.analog-innovations.com           |    1962     |
             
I love to cook with wine.      Sometimes I even put it in the food.
Reply to
Jim Thompson

Yes, now that you mention it, but only from having seen it in re-runs, that I'll admit to. :>)

Yep, full synchronous is the way to go, but with '160 you're up two more in the chip count. These days we turn to PLDs for this stuff: everything in one chip. Or a uP, if timing accuracy doesn't matter.

This means we just show a box with some wires going in and out, and specify that the programming is left as an exercise for the reader.

Congrats all round, of course! Lesseee, was she a teenage bride?

Thanks, - Win

whill_at_picovolt-dot-com

Reply to
Winfield Hill

[snip]

Yep, one of those marriages that wasn't supposed to last, I was 20, "N" was 18. (And I was still a Sophomore at MIT.)

...Jim Thompson

--
|  James E.Thompson, P.E.                           |    mens     |
|  Analog Innovations, Inc.                         |     et      |
|  Analog/Mixed-Signal ASIC's and Discrete Systems  |    manus    |
|  Phoenix, Arizona            Voice:(480)460-2350  |             |
|  E-mail Address at Website     Fax:(480)460-2142  |  Brass Rat  |
|       http://www.analog-innovations.com           |    1962     |
             
I love to cook with wine.      Sometimes I even put it in the food.
Reply to
Jim Thompson 

--
Puhleeezeee!!!

For simple stuff, you've got 12 bits to work with with a 4040, and
four with a 160.  One chip against three... it's like golf, the
smaller number wins.
Reply to
John Fields

You shouldn't assume that uP's are only useful if timing doesn't matter. I just did a uP generating 5 frequencies simultaneously (in the low kHz to high hundreds of Hz) with NO jitter (for some of us anyway, I'm sure JL would see scads of jitter as the xtal oscillator jitters a bit) and frequency resolution of one clock cycle. Of course that's using peripheral hardware on the chip, but on the plus side, it's ALL on the chip.

Teeeeedyusss.

Indeed. Congratulations. We're only 1/3 of the way there. ;-)

Best regards, Spehro Pefhany

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Reply to
Spehro Pefhany

I knew that! Having done it myself, but forgotten. Sheesh!

Thanks, - Win

whill_at_picovolt-dot-com

Reply to
Winfield Hill

VitaMeataVegamin

It has vitamins and meat and vegetables, and apparently some liquor.

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Reply to
Tom Del Rosso

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Reply to
GPG

Actually, you can have the best of two worlds by putting the Dff inside the feedback loop. Might as well take advantage of the fact that HC74s come in pairs (prevents having to decode an odd number). Here is how:

  1. delete the hc04.
  2. connect the hc20 output to D of first hc74
  3. connect Q of first hc74 to D of second hc74
  4. decode 3558
  5. connect all clock inputs together.
  6. connect Q* of second hc74 to RESET of hc4020
  7. connect Q of second hc74 to SET of first hc74

Tam

Reply to
Tam/WB2TT

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