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Delaying a logic signal?

Hi, I'm designing a simple (ha!) digital oscilloscope that should theoretically be able to sample up to 80MHz with two A/D converters (giving an effective frequency of around 160 MHz). I'd also like to design this device so I can expand it with more converters later on (up to four). What I need to know is how to delay a logic signal (the /SAMPLE line) so that it's 90 degrees out of phase. Then I need another two in addition to that - 180deg and 270deg. The signal needs to be as close to 50% as possible. How could I do this? None of my textbooks seem to cover this sort of thing. The idea is that I'll have multiple ADCs sampling at different times, one after the other. The data will end up in a FIFO, which will then be read by the PC via the ISA bus. I'm also going to need a programmable clock divider that can provide various frequencies to the ADCs. I guess this would be best done with a counter and a multiplexer?

Thanks.

--
Phil.                                | Acorn RiscPC600 Mk3, SA202, 64MB,
philpem@despammed.com (valid address)| 6GB, video mods, 8xCD, framegrabber,
http://www.philpem.dsl.pipex.com/    | Ethernet (i3 Etherlan600), Teletext
Seen on T-shirts at NASA: WILL BUILD SPACE STATION FOR FOOD.
Reply to
Philip Pemberton
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Lots of ways..

Try using a counter to steer the master Sample signal to the output of a 2 to 4 decoder.

This produces a pulse on each output in turn eg

1000 0100 0010 0001 1000 0100 etc

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Reply to
CWatters

Actually you want to be able to control the timing of the sample pulses more accuratly than that. Ideally you want to be able to adjust the interval between triggering and sampling perhaps a down to a nS?. That way you can sample repetitive signals (only) that are much faster than the sample rate. eg you can display a 200MHz sin wave even ifyou only have 85Mhz ADC's.

Do a google for "PC oscilloscope" and read about existing designs including at least two kits that are available.

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Reply to
CWatters

That sounds like the best (cheapest) option - get an SRAM FPGA (or an EEPLD) and put the glue logic inside it. I don't mind being stuck at 10nS - my Tek466 only goes down to .05uS anyway.

That's going to be, er... "fun"...

Thanks.

--
Phil.                                | Acorn RiscPC600 Mk3, SA202, 64MB,
philpem@despammed.com (valid address)| 6GB, video mods, 8xCD, framegrabber,
http://www.philpem.dsl.pipex.com/    | Ethernet (i3 Etherlan600), Teletext
... I will not steal this tagline, it eez scratched.
Reply to
Philip Pemberton

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