Hi
I have an 18-bit bus to a ZBT memory but when I P&R it in Xilinx it set half the bus to TRISTATE and the other to BIDIR. Is this to do with the I placement or something else? In Synplify they all come up as IOBUF
Cheers
J
I'd check the map report to see if the TRISTATE half of the bus lost its input path due to removed (optimised away) logic. Sometimes logic is removed due to lack of visible outputs from some other logic further down the line, so it wouldn't be obvious at first that the logic is "unnecessary".
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