Z-busses and synthesis

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Hello all,

I'm curious if anyone happens to know how the Xilinx and Altera tools,
in particular, handle Z-values for internal signals.  If one has a
collection of modules which use bidirectional tristate busses, can one
combine them in the obvious way and have the synthesis program create
whatever logic is needed to simulate the wired-MUXness of the tristate
bus, or do one have to explicitly recode everything to use gates or


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Re: Z-busses and synthesis

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Using schematic entry to Xilinx Foundation and ISE, I have done this
both in CPLDs (XC9500 series) and in Spartan FPGAs.  The FPGAs can
do it directly in hardware, I think the CPLDs simulate the logic function
with gates that assume a logic 1 on the bus if no BUFT is driving it.
That's not a condition you'd really want to allow, anyway, for some poor
soul reading the docs later.


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