Hello all,
I'm curious if anyone happens to know how the Xilinx and Altera tools, in particular, handle Z-values for internal signals. If one has a collection of modules which use bidirectional tristate busses, can one combine them in the obvious way and have the synthesis program create whatever logic is needed to simulate the wired-MUXness of the tristate bus, or do one have to explicitly recode everything to use gates or muxes?
Thanks,
-hpa