Good day,
I'm sorry to start another thread on the notorious NGDBUILD 455 problem while using Xilinx ISE, however I simply can't figure out the solutions based on what I read on the web. My scenario is that I have some sub-sub-modules (SSMs) synthesized with Synplify. I've disabled I/O insertion. Then in ISE 6.1, I use a sub-module (SM?), which is a Verilog file, as the top module for those synthesized SSMs. However there is a real top module (TM, also a Verilog file), which encompasses my SM and other SMs.
Therefore
TM (.v) ____|___________ | \ \ | \ \ SM-1 SM-2 ... (.v) |_______________ | \ \ SSM-1 SSM-2 ... (.edf)
My problem then occurs when ISE tries to translate my design. The major part is that my RESET has NGDBUILD 455 (multiple drivers) and 466 (multiple buffers) errors. And the major reason I can think of is that I do lots of the following: wire reset_xx = RESET;
The RESET signal comes externally to TM, and then drives through SM-1 to those SSMs. I've tried to disabled "Add I/O Buffers" in the Synthesis option, but the results remain the same.
Is my assignment illegal? I think that it's quite natural to "rename" the RESET signal since each module can be designed by different people. Or should I just stop the maddness and let RESET be RESET?
Please give me any comments you have. Thank you :-)
Regards, MJ