Hello! So the only ucf timing-related constraint I've ever really had cause to use is the PERIOD constraint, such as:
NET "CLKIN" TNM_NET = "CLKIN"; TIMESPEC "TS_CLKIN" = PERIOD "CLKIN" 19.9 ns HIGH 50 %;
I remember reading somewhere on the xilinx supprt site that you should always give yourself several hundred ps of wiggle-room, but I also remember reading that the tools take into account process and temp variations and so I should never try and be over-agressive in my timing constraints.
Does anyone have any experience one way or the other that they can share? What is your constraint strategy? I notice that the synthesis of my designs tends to be pretty sensitive to the actual constraint value -- devices that that synth at 19.8 ns might not at 19.9, even though it is a "slower" design.
Thanks! ...Eric