Hello All! We're working with a Xilinx Virtex II Pro board. As a part of our project, we had to write a hardware stack. After having made it work, we thought of optimizing the design and hence removed a few states and reduced the no. of states from 8 to 4. The older code was getting synthesized in around 20 mins, but the new code takes hours together to get synthesized, and so does the PAR. How can we reduce the synthesis time? Why is that the code which took lesser time to get synthesized is now taking longer?
-- DotNetters.