I've been bitten several times by XST producing sub-optimal results by trying to use the flip-flop enable when it doesn't need to. We all know the priority of Reset/Set/Enable to ensure that the flip-flop pins can be used, but if you need to violate this, then XST may create stupid logic.
For example:
always @(posedge Clk10 or posedge reset) if (reset) timeout_intr_reg
Hi John,
Yes, XST gets this "wrong" sometimes (more often than not, I'd say, when you're designing for a reasonably high speed). It does the same thing with synchronous sets and resets, too.
You might find the synthesis constraints "use_clock_enable", "use_sync_reset" and "use_sync_set" to be useful. In your case, the invocation would be (I think):
// synthesis attribute use_clock_enable of timeout_instr_reg is no;
That should allow you to keep your nice readable RTL description intact, but not suffer timing problems. (I'm not saying this is ideal, but anything that solves your problem, right? :-)).
Cheers,
-Ben-
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