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xst synthesis

Hi, I am having problems with XST Synthesis from Xilinx. When synthesizing a unit from my created IP, the synthesis tool just stops, providing no error explanation. The last messages I get from the log files are the following: Synthesizing Unit . Related source file is //hamurabi.iro.umontreal.ca/brassaro/projet/Systeme_Test/pcores/pow_function_v1_00_a/hdl/vhdl/DEV4_uid101.vhd. WARNING:Xst:647 - Input is never used. WARNING:Xst:647 - Input is never used. WARNING:Xst:647 - Input is never used. WARNING:Xst:647 - Input is never used. WARNING:Xst:647 - Input is never used. WARNING:Xst:647 - Input is never used. WARNING:Xst:647 - Input is never used. WARNING:Xst:647 - Input is never used. WARNING:Xst:647 - Input is never used. WARNING:Xst:647 - Input is never used. Found finite state machine for signal .

----------------------------------------------------------------------- | States | 12 | | Transitions | 25 | | Inputs | 13 | | Outputs | 12 | | Clock | u_sid95_sid88_sid98_uid2705 (rising_edge) | | Clock enable | S122_sid103_sid2164_sid2166_sid102_sid2167_uid2961 (positive) | | Power Up State | fsl_interface_start | | Encoding | automatic | | Implementation | automatic |

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Please help!!! Thank you

Reply to
brassaro
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Forgot to mention that i am using EDK 6.3i.

Reply to
brassaro

Check the synthesis report for details, if you have not already done so. Sometimes errors don't appear inthe dialog but in the report for which there are various in ISE. Also, check to see if your connections are complete, perhaps none are recognized. If all fails try opening a web support issue with Xilinx. This can take time but the response often hits the heart ofthe problem.

-Andrew

Reply to
Andrew Lohbihler

I checked the reports, and no other info except the one I posted is given. What bothers me also is that synthesis works on altera tools, like Quartus II. Could it be an error that Quartus does not find in the design, or is it a bug in Xilinx tools?

Reply to
brassaro

Found a way to synthesize... Set the fsm_extract flag to false. Seems like FSM extraction does not work for my design!

Reply to
brassaro

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