I guess this is more of a Xilinx question than a VHDL question. Anyways, once again, I find myself wanting to set the value of a generic on the top-level of my chip design from the synthesis tool -- XST, in this case -- either from the GUI or from the command line.
Replying to myself ... I received the following from Xilinx Support:
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----------------------------------------- "*** EMAIL OUT AND STATUS CHANGE 06/30/2005 03:08:55 xud Action Type: External email Send to: [External Contact] Dear Andy Peters,
Thank you for choosing Xilinx Customer Support! My name is Sally Dong and I will be helping you to resolve your issue. I can be reached via email at External Contact.
I have tried searching for the XST function of changing generics at synthesis time and I can not find such one. The XST may not support it.
Please let me know if this did not address your concern, or if you have any questions on this issue.
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So XST doesn't support a language feature that all of the other synthesis tools (including, BTW, Altera Quartus') support and in most cases have supports since they started using FPGAs for logic synthesis?
I'm rather amazed that few people use this feature.
Hey, Peter and Austin -- kick someone's ass over at the XST Features Department.
-a
PS: for my current problem, my solution is to simply create a stupid little outputs-only entity; each output corresponds to the generic I wish to set. If I have two version of my design, I have two different files, each containing a different version of the entity. The entity is given the same name in both files, so when it's used to build the design, nothing has to change in the main sources, and my XST script for each version uses only one of the two files.
Andy, for a long time none of the synthesis tools supported this. The work-around I use is I create a separate file containing a VHDL package with the parameters I want to be able to change in it, and then reference the package in my main code. That way, you change the parameters in the defaults.vhd package file and it gets reflected in the real design. Here is an example:
in your design files that need the settings (just the top level design if you then pass these down the hierarchy through generics) put the library declarations: library work; use work.settings.all;
which makes all the constants (and functions too) defined in the package available.
Then in settings.vhd you declare the package: package settings is constant in_coefs1:int_array(0 to 2):= (-4,-8,56); --v27 constant in_coefs0:int_array(0 to 2):= (-2,-4,32); --v27
-- constant in_coefs1:int_array(0 to 2):= (-4,-4,40); --v25,26 coefs
-- constant in_coefs0:int_array(0 to 2):= (-2,-2,24); --v25,26 coefs
-- constant in_coefs0:int_array(0 to 2):= (-1,-1,16);
-- constant in_coefs1:int_array(0 to 2):= (-2,-2,24);
-- constant out_coefs0:int_array(0 to 2):= (1,3,16); --v25,26 coefs
This gives you far more flexibility than generics do. I've even gone as far as writing a 'C' application to automatically generate the settings.vhd file as a result of entries in a windoze dialog box. A package file generated by C, matlab or some other language capable of trig functions or whatnot, or from an excel spreadsheet even is a way to get tables of constants that are not easy to generate in synthesizable VHDL into the design. That comes up when you have a synthesis tool that doesn't recognize reals and you need a table of trig values to initialize a ROM, for example. You can also use a VHDL testbench to generate such a file, since the generating program doesn't go through the synthesis (which means you can use reals).
--
--Ray Andraka, P.E.
President, the Andraka Consulting Group, Inc.
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