OK, so I'm trying to synthesize a huge design. Just for quick reference, the inferred macros are below:
HDL Synthesis Report
Macro Statistics # Block RAMs : 112 16x24-bit dual-port block RAM : 64 1024x12-bit single-port block RAM : 48 # ROMs : 3 16x10-bit ROM : 3 # Multipliers : 480 12x12-bit registered multiplier : 480 # Adders/Subtractors : 3856 10-bit adder : 20 8-bit adder : 32 9-bit adder : 16 7-bit adder : 16 12-bit adder : 1792 24-bit adder : 480 12-bit subtractor : 1472 4-bit subtractor : 15 5-bit adder : 1 4-bit adder : 12 # Counters : 1 5-bit up counter : 1 # Registers : 13434 4-bit register : 30 24-bit register : 577 12-bit register : 480 10-bit register : 20 5-bit register : 1 1-bit register : 12325 3-bit register : 1 # Comparators : 44 10-bit comparator greatequal : 12 5-bit comparator lessequal : 2 5-bit comparator greater : 2 10-bit comparator greater : 7 10-bit comparator less : 11 10-bit comparator lessequal : 8 5-bit comparator greatequal : 1 5-bit comparator less : 1 # Multiplexers : 1070 4-bit 2-to-1 multiplexer : 10 1-bit 2-to-1 multiplexer : 2 12-bit 2-to-1 multiplexer : 1040 24-bit 2-to-1 multiplexer : 1 24-bit 64-to-1 multiplexer : 1 24-bit 16-to-1 multiplexer : 16 # Xors : 480 1-bit xor2 : 480
The code is fairly well-optimized and functionally correct. However, it is a huge design, and it should be about 47,000 SLICEs once all is said and done. But, alas:
"ERROR: Portability:3 - This Xilinx application has run out of memory or has encountered a memory conflict..."
I'm sure plenty of you have gotten this error before. On a machine with 2.5 GB of memory and dual 3.0 GHz processors, should I be getting this error? I've been working on optimizing my code but I was wondering if there is a point where the design is simply too large.