XST (ISE 6.1i): Error: It's interesting and surprising

Hi guys.

An intesresting problem occured when I used "more than three" signals in always block sens list.

XST (ISE 6.1i) reported the following error:

ERROR:Xst:1468 - dummy.v line 25: Unexpected event in always block sensitivity list.

Same code is successfully compiled & simulated in MOdelSim5.7SE.

What kind of problem is this ? Related to parser/editor/etc ??

//-------- C O D E - C O D E --------///

module dummy(x); output x; assign x = 1'b0;

reg a,b,c,d; reg z;

initial begin a=0; b=0; c=0; d=0; z=0; #100 $stop; end

always #10 a=~a; always #15 b=~b; always #20 c=~c; always #5 d=~d;

always @(posedge a or posedge b or posedge c or posedge d ) begin if(a) z=~z; else if(b)z=~z; else if(c) z=~z; else if(d) z=~z; end endmodule

Reply to
QRaheeL
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Your results are not surprising. Although your code is legal Verilog and is able to simulate, it's not synthesizable. What type of flip-flop would you expect XST to infer from the "always @(posedge a or posedge b or posedge c or posedge d ) " construct?

You need to re-think your code!

Good luck!

John Providenza

Reply to
johnp

What flip-flop has four clocks?

-a

Reply to
Andy Peters

what the hell is this? quad-clock flip-flop?

V
Reply to
Vladislav Muravin

Dunno, but just imagine the phantasmagorical metastability polemic that such a Machiavellian device would foment! Cheers, Syms.

Reply to
Symon

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