Hi all,
Maybe this question has been asked before, but I couldn't find a suitable answer on this group until now. Having followed the coding styles recommended by Xilinx, I ended up with the following code:
library IEEE; use IEEE.std_logic_1164.all; use IEEE.numeric_std.all;
entity dual_port_ram is generic ( WIDTH : integer := 32; DEPTH : integer := 10 ); port ( w_clk : in std_logic; w_en_in : in std_logic; w_addr_in : in std_logic_vector(DEPTH-1 downto 0); w_data_in : in std_logic_vector(WIDTH-1 downto 0);
r_clk : in std_logic; r_addr_in : in std_logic_vector(DEPTH-1 downto 0); r_data_out : out std_logic_vector(WIDTH-1 downto 0) ); end entity;
architecture xilinx of dual_port_ram is
type memory_type is array (natural range ) of std_logic_vector(WIDTH-1 downto 0); signal memory : memory_type(2**DEPTH-1 downto 0);
begin
write : process(w_clk) begin if w_clk'event and w_clk = '1' then if w_en_in = '1' then memory(to_integer(unsigned(w_addr_in)))