Hi,
i have a state machine like this
always @( * ) case(state) IDLE: casex(SOME_STATEMENTS) {inputs}: next = NEXT_STATE1; {inputs}: next = NEXT_STATE3; default: next = IDLE; STATE1; casex(SOME_STATEMENTS) {inputs}: next = STATE2; {inputs}: next = STATE4; default: next = STATE1; default: next = IDLE;
In functional simulation everything is fine. After XST synthesis magical things happen. THe FSM just doesn't work correctly anymore logically. Some inputs are misinterpreted causing the FSM to jump into wrong states. It's ridiculous. The output signals for the specific states however are correct.
FSM encoding USER did not help however disabling FSM encoding by setting it to NONE in the XST properties helped. Now the design runs fine after XST. It is however 3 MHz slower. Worse is that you cannot trust the XST anymore at all.
Is this a known problem? Maybe its just the coding style which confuses the XST.