XST bug inferring dynamic shift register

Hi,

I've got the following Verilog code which selects a variable tap from a delay line:

wire [2:0] idly; reg signed [dsz-1:0] d0, d1, d2, d3, d4, d5, d6, d7; reg signed [dsz-1:0] id;

always @(posedge clk) begin d0